@@ -274,19 +274,19 @@ attributes #0 = { nounwind readnone }
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; ARMPL-SAME: _ZGVsMxvl4_modff(armpl_svmodf_f32_x)" }
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; ARMPL: attributes #[[SIN]] = { "vector-function-abi-variant"=
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; ARMPL-SAME: "_ZGV_LLVM_N2v_sin(armpl_vsinq_f64),
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- ; ARMPL-SAME _ZGVsMxv_sin(armpl_svsin_f64_x)" }
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+ ; ARMPL-SAME: _ZGVsMxv_sin(armpl_svsin_f64_x)" }
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; ARMPL: attributes #[[SINCOS]] = { "vector-function-abi-variant"=
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; ARMPL-SAME: "_ZGV_LLVM_N2vl8l8_sincos(armpl_vsincosq_f64),
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- ; ARMPL-SAME: _ZGVsMxvl8l8_sincos(armpl_svsincos_f64_x)" }
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+ ; ARMPL-SAME: _ZGVsMxvl8l8_sincos(armpl_svsincos_f64_x)" }
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; ARMPL: attributes #[[SINCOSF]] = { "vector-function-abi-variant"=
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; ARMPL-SAME: "_ZGV_LLVM_N4vl4l4_sincosf(armpl_vsincosq_f32),
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; ARMPL-SAME: _ZGVsMxvl4l4_sincosf(armpl_svsincos_f32_x)" }
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; ARMPL: attributes #[[SINCOSPI]] = { "vector-function-abi-variant"=
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; ARMPL-SAME: "_ZGV_LLVM_N2vl8l8_sincospi(armpl_vsincospiq_f64),
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- ; ARMPL-SAME: _ZGVsMxvl8l8_sincospi(armpl_svsincospi_f64_x)" }
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+ ; ARMPL-SAME: _ZGVsMxvl8l8_sincospi(armpl_svsincospi_f64_x)" }
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; ARMPL: attributes #[[SINCOSPIF]] = { "vector-function-abi-variant"=
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; ARMPL-SAME: "_ZGV_LLVM_N4vl4l4_sincospif(armpl_vsincospiq_f32),
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; ARMPL-SAME: _ZGVsMxvl4l4_sincospif(armpl_svsincospi_f32_x)" }
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; ARMPL: attributes #[[LOG10]] = { "vector-function-abi-variant"=
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; ARMPL-SAME: "_ZGV_LLVM_N4v_llvm.log10.f32(armpl_vlog10q_f32),
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- ; ARMPL-SAME _ZGVsMxv_llvm.log10.f32(armpl_svlog10_f32_x)" }
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+ ; ARMPL-SAME: _ZGVsMxv_llvm.log10.f32(armpl_svlog10_f32_x)" }
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