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Pierre-vhPierre-vh
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[AMDGPU] New RegBankSelect: Add missing S/VGPR pointer types
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3 files changed

+65
-0
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3 files changed

+65
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‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -557,10 +557,14 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
557557
case Vgpr64:
558558
return LLT::scalar(64);
559559
case VgprP0:
560+
case SgprP0:
560561
return LLT::pointer(0, 64);
561562
case SgprP1:
562563
case VgprP1:
563564
return LLT::pointer(1, 64);
565+
case SgprP2:
566+
case VgprP2:
567+
return LLT::pointer(2, 32);
564568
case SgprP3:
565569
case VgprP3:
566570
return LLT::pointer(3, 32);
@@ -570,6 +574,12 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
570574
case SgprP5:
571575
case VgprP5:
572576
return LLT::pointer(5, 32);
577+
case SgprP6:
578+
case VgprP6:
579+
return LLT::pointer(6, 32);
580+
case SgprP8:
581+
case VgprP8:
582+
return LLT::pointer(8, 128);
573583
case SgprV2S16:
574584
case VgprV2S16:
575585
case UniInVgprV2S16:
@@ -646,10 +656,14 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
646656
case Sgpr16:
647657
case Sgpr32:
648658
case Sgpr64:
659+
case SgprP0:
649660
case SgprP1:
661+
case SgprP2:
650662
case SgprP3:
651663
case SgprP4:
652664
case SgprP5:
665+
case SgprP6:
666+
case SgprP8:
653667
case SgprV2S16:
654668
case SgprV2S32:
655669
case SgprV4S32:
@@ -680,9 +694,12 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
680694
case Vgpr64:
681695
case VgprP0:
682696
case VgprP1:
697+
case VgprP2:
683698
case VgprP3:
684699
case VgprP4:
685700
case VgprP5:
701+
case VgprP6:
702+
case VgprP8:
686703
case VgprV2S16:
687704
case VgprV2S32:
688705
case VgprV4S32:
@@ -718,10 +735,14 @@ void RegBankLegalizeHelper::applyMappingDst(
718735
case Sgpr16:
719736
case Sgpr32:
720737
case Sgpr64:
738+
case SgprP0:
721739
case SgprP1:
740+
case SgprP2:
722741
case SgprP3:
723742
case SgprP4:
724743
case SgprP5:
744+
case SgprP6:
745+
case SgprP8:
725746
case SgprV2S16:
726747
case SgprV2S32:
727748
case SgprV4S32:
@@ -730,9 +751,12 @@ void RegBankLegalizeHelper::applyMappingDst(
730751
case Vgpr64:
731752
case VgprP0:
732753
case VgprP1:
754+
case VgprP2:
733755
case VgprP3:
734756
case VgprP4:
735757
case VgprP5:
758+
case VgprP6:
759+
case VgprP8:
736760
case VgprV2S16:
737761
case VgprV2S32:
738762
case VgprV4S32: {
@@ -839,10 +863,14 @@ void RegBankLegalizeHelper::applyMappingSrc(
839863
case Sgpr16:
840864
case Sgpr32:
841865
case Sgpr64:
866+
case SgprP0:
842867
case SgprP1:
868+
case SgprP2:
843869
case SgprP3:
844870
case SgprP4:
845871
case SgprP5:
872+
case SgprP6:
873+
case SgprP8:
846874
case SgprV2S16:
847875
case SgprV2S32:
848876
case SgprV4S32: {
@@ -867,9 +895,12 @@ void RegBankLegalizeHelper::applyMappingSrc(
867895
case Vgpr64:
868896
case VgprP0:
869897
case VgprP1:
898+
case VgprP2:
870899
case VgprP3:
871900
case VgprP4:
872901
case VgprP5:
902+
case VgprP6:
903+
case VgprP8:
873904
case VgprV2S16:
874905
case VgprV2S32:
875906
case VgprV4S32: {

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -54,12 +54,18 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
5454
return MRI.getType(Reg) == LLT::pointer(0, 64);
5555
case P1:
5656
return MRI.getType(Reg) == LLT::pointer(1, 64);
57+
case P2:
58+
return MRI.getType(Reg) == LLT::pointer(2, 32);
5759
case P3:
5860
return MRI.getType(Reg) == LLT::pointer(3, 32);
5961
case P4:
6062
return MRI.getType(Reg) == LLT::pointer(4, 64);
6163
case P5:
6264
return MRI.getType(Reg) == LLT::pointer(5, 32);
65+
case P6:
66+
return MRI.getType(Reg) == LLT::pointer(6, 32);
67+
case P8:
68+
return MRI.getType(Reg) == LLT::pointer(8, 128);
6369
case V2S32:
6470
return MRI.getType(Reg) == LLT::fixed_vector(2, 32);
6571
case V4S32:
@@ -88,12 +94,18 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
8894
return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isUniform(Reg);
8995
case UniP1:
9096
return MRI.getType(Reg) == LLT::pointer(1, 64) && MUI.isUniform(Reg);
97+
case UniP2:
98+
return MRI.getType(Reg) == LLT::pointer(2, 32) && MUI.isUniform(Reg);
9199
case UniP3:
92100
return MRI.getType(Reg) == LLT::pointer(3, 32) && MUI.isUniform(Reg);
93101
case UniP4:
94102
return MRI.getType(Reg) == LLT::pointer(4, 64) && MUI.isUniform(Reg);
95103
case UniP5:
96104
return MRI.getType(Reg) == LLT::pointer(5, 32) && MUI.isUniform(Reg);
105+
case UniP6:
106+
return MRI.getType(Reg) == LLT::pointer(6, 32) && MUI.isUniform(Reg);
107+
case UniP8:
108+
return MRI.getType(Reg) == LLT::pointer(8, 128) && MUI.isUniform(Reg);
97109
case UniV2S16:
98110
return MRI.getType(Reg) == LLT::fixed_vector(2, 16) && MUI.isUniform(Reg);
99111
case UniB32:
@@ -120,12 +132,18 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
120132
return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isDivergent(Reg);
121133
case DivP1:
122134
return MRI.getType(Reg) == LLT::pointer(1, 64) && MUI.isDivergent(Reg);
135+
case DivP2:
136+
return MRI.getType(Reg) == LLT::pointer(2, 32) && MUI.isDivergent(Reg);
123137
case DivP3:
124138
return MRI.getType(Reg) == LLT::pointer(3, 32) && MUI.isDivergent(Reg);
125139
case DivP4:
126140
return MRI.getType(Reg) == LLT::pointer(4, 64) && MUI.isDivergent(Reg);
127141
case DivP5:
128142
return MRI.getType(Reg) == LLT::pointer(5, 32) && MUI.isDivergent(Reg);
143+
case DivP6:
144+
return MRI.getType(Reg) == LLT::pointer(6, 32) && MUI.isDivergent(Reg);
145+
case DivP8:
146+
return MRI.getType(Reg) == LLT::pointer(8, 128) && MUI.isDivergent(Reg);
129147
case DivV2S16:
130148
return MRI.getType(Reg) == LLT::fixed_vector(2, 16) && MUI.isDivergent(Reg);
131149
case DivB32:

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,21 +53,30 @@ enum UniformityLLTOpPredicateID {
5353
// pointers
5454
P0,
5555
P1,
56+
P2,
5657
P3,
5758
P4,
5859
P5,
60+
P6,
61+
P8,
5962

6063
UniP0,
6164
UniP1,
65+
UniP2,
6266
UniP3,
6367
UniP4,
6468
UniP5,
69+
UniP6,
70+
UniP8,
6571

6672
DivP0,
6773
DivP1,
74+
DivP2,
6875
DivP3,
6976
DivP4,
7077
DivP5,
78+
DivP6,
79+
DivP8,
7180

7281
// vectors
7382
V2S16,
@@ -117,10 +126,14 @@ enum RegBankLLTMappingApplyID {
117126
Sgpr16,
118127
Sgpr32,
119128
Sgpr64,
129+
SgprP0,
120130
SgprP1,
131+
SgprP2,
121132
SgprP3,
122133
SgprP4,
123134
SgprP5,
135+
SgprP6,
136+
SgprP8,
124137
SgprV2S16,
125138
SgprV4S32,
126139
SgprV2S32,
@@ -137,9 +150,12 @@ enum RegBankLLTMappingApplyID {
137150
Vgpr64,
138151
VgprP0,
139152
VgprP1,
153+
VgprP2,
140154
VgprP3,
141155
VgprP4,
142156
VgprP5,
157+
VgprP6,
158+
VgprP8,
143159
VgprV2S16,
144160
VgprV2S32,
145161
VgprB32,

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