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[RISCV] Add reusable SelectCC_GPR_riirr multiclass. NFC (#140224)
Add reusable SelectCC_GPR_riirr multiclass. Allow Select_GPR_Using_CC_* in XCV and Xqci to share a commom multiclass implmentation.
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5 files changed

+34
-40
lines changed

5 files changed

+34
-40
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -21018,7 +21018,7 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
2101821018

2101921019
auto Next = next_nodbg(MI.getIterator(), BB->instr_end());
2102021020
if ((MI.getOpcode() != RISCV::Select_GPR_Using_CC_GPR &&
21021-
MI.getOpcode() != RISCV::Select_GPR_Using_CC_Imm) &&
21021+
MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5) &&
2102221022
Next != BB->end() && Next->getOpcode() == MI.getOpcode() &&
2102321023
Next->getOperand(5).getReg() == MI.getOperand(0).getReg() &&
2102421024
Next->getOperand(5).isKill())
@@ -21351,11 +21351,11 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
2135121351
"ReadCounterWide is only to be used on riscv32");
2135221352
return emitReadCounterWidePseudo(MI, BB);
2135321353
case RISCV::Select_GPR_Using_CC_GPR:
21354-
case RISCV::Select_GPR_Using_CC_Imm:
21355-
case RISCV::Select_GPR_Using_CC_Simm5NonZero:
21356-
case RISCV::Select_GPR_Using_CC_Uimm5NonZero:
21357-
case RISCV::Select_GPR_Using_CC_Simm16NonZero:
21358-
case RISCV::Select_GPR_Using_CC_Uimm16NonZero:
21354+
case RISCV::Select_GPR_Using_CC_SImm5:
21355+
case RISCV::Select_GPR_Using_CC_SImm5NonZero:
21356+
case RISCV::Select_GPR_Using_CC_UImm5NonZero:
21357+
case RISCV::Select_GPR_Using_CC_SImm16NonZero:
21358+
case RISCV::Select_GPR_Using_CC_UImm16NonZero:
2135921359
case RISCV::Select_FPR16_Using_CC_GPR:
2136021360
case RISCV::Select_FPR16INX_Using_CC_GPR:
2136121361
case RISCV::Select_FPR32_Using_CC_GPR:

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1646,6 +1646,14 @@ let Predicates = [HasStdExtC, OptForMinSize] in {
16461646
def : SelectCompressOpt<SETNE>;
16471647
}
16481648

1649+
multiclass SelectCC_GPR_riirr<DAGOperand valty, DAGOperand imm> {
1650+
let usesCustomInserter = 1 in
1651+
def Select_GPR_Using_ # NAME
1652+
: Pseudo<(outs valty:$dst),
1653+
(ins GPR:$lhs, imm:$imm, cond_code:$cc,
1654+
valty:$truev, valty:$falsev), []>;
1655+
}
1656+
16491657
/// Branches and jumps
16501658

16511659
// Match `riscv_brcc` and lower to the appropriate RISC-V branch instruction.

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -802,16 +802,12 @@ let Predicates = [HasVendorXCVbi, IsRV32], AddedComplexity = 2 in {
802802
def : Pat<(riscv_brcc GPR:$rs1, simm5:$imm5, SETNE, bb:$imm12),
803803
(CV_BNEIMM GPR:$rs1, simm5:$imm5, bare_simm13_lsb0:$imm12)>;
804804

805-
let usesCustomInserter = 1 in
806-
def Select_GPR_Using_CC_Imm : Pseudo<(outs GPR:$dst),
807-
(ins GPR:$lhs, simm5:$imm5, cond_code:$cc,
808-
GPR:$truev, GPR:$falsev), []>;
809-
805+
defm CC_SImm5 : SelectCC_GPR_riirr<GPR, simm5>;
810806

811807
class Selectbi<CondCode Cond>
812808
: Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), simm5:$Constant, Cond,
813809
(i32 GPR:$truev), GPR:$falsev),
814-
(Select_GPR_Using_CC_Imm GPR:$lhs, simm5:$Constant,
810+
(Select_GPR_Using_CC_SImm5 GPR:$lhs, simm5:$Constant,
815811
(IntCCtoRISCVCCCV $cc), GPR:$truev, GPR:$falsev)>;
816812

817813
def : Selectbi<SETEQ>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Lines changed: 17 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1327,20 +1327,10 @@ class Bcci48Pat<CondCode Cond, QCIBranchInst48_rii Inst, DAGOperand InTyImm>
13271327
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
13281328
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0:$imm12)>;
13291329

1330-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, usesCustomInserter = 1 in {
1331-
def Select_GPR_Using_CC_Simm5NonZero : Pseudo<(outs GPR:$dst),
1332-
(ins GPR:$lhs, simm5nonzero:$imm5,
1333-
cond_code:$cc, GPR:$truev, GPR:$falsev), []>;
1334-
def Select_GPR_Using_CC_Uimm5NonZero : Pseudo<(outs GPR:$dst),
1335-
(ins GPR:$lhs, uimm5nonzero:$imm5,
1336-
cond_code:$cc, GPR:$truev, GPR:$falsev), []>;
1337-
def Select_GPR_Using_CC_Simm16NonZero : Pseudo<(outs GPR:$dst),
1338-
(ins GPR:$lhs, simm16nonzero:$imm16,
1339-
cond_code:$cc, GPR:$truev, GPR:$falsev), []>;
1340-
def Select_GPR_Using_CC_Uimm16NonZero : Pseudo<(outs GPR:$dst),
1341-
(ins GPR:$lhs, uimm16nonzero:$imm16,
1342-
cond_code:$cc, GPR:$truev, GPR:$falsev), []>;
1343-
}
1330+
defm CC_SImm5NonZero : SelectCC_GPR_riirr<GPR, simm5nonzero>;
1331+
defm CC_UImm5NonZero : SelectCC_GPR_riirr<GPR, uimm5nonzero>;
1332+
defm CC_SImm16NonZero : SelectCC_GPR_riirr<GPR, simm16nonzero>;
1333+
defm CC_UImm16NonZero : SelectCC_GPR_riirr<GPR, uimm16nonzero>;
13441334

13451335
class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
13461336
: Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), InTyImm:$Constant, Cond,
@@ -1419,19 +1409,19 @@ def : Bcci48Pat<SETGE, QC_E_BGEI, simm16nonzero>;
14191409
def : Bcci48Pat<SETULT, QC_E_BLTUI, uimm16nonzero>;
14201410
def : Bcci48Pat<SETUGE, QC_E_BGEUI, uimm16nonzero>;
14211411

1422-
def : SelectQCbi<SETEQ, simm5nonzero, Select_GPR_Using_CC_Simm5NonZero>;
1423-
def : SelectQCbi<SETNE, simm5nonzero, Select_GPR_Using_CC_Simm5NonZero>;
1424-
def : SelectQCbi<SETLT, simm5nonzero, Select_GPR_Using_CC_Simm5NonZero>;
1425-
def : SelectQCbi<SETGE, simm5nonzero, Select_GPR_Using_CC_Simm5NonZero>;
1426-
def : SelectQCbi<SETULT, uimm5nonzero, Select_GPR_Using_CC_Uimm5NonZero>;
1427-
def : SelectQCbi<SETUGE, uimm5nonzero, Select_GPR_Using_CC_Uimm5NonZero>;
1428-
1429-
def : SelectQCbi<SETEQ, simm16nonzero, Select_GPR_Using_CC_Simm16NonZero>;
1430-
def : SelectQCbi<SETNE, simm16nonzero, Select_GPR_Using_CC_Simm16NonZero>;
1431-
def : SelectQCbi<SETLT, simm16nonzero, Select_GPR_Using_CC_Simm16NonZero>;
1432-
def : SelectQCbi<SETGE, simm16nonzero, Select_GPR_Using_CC_Simm16NonZero>;
1433-
def : SelectQCbi<SETULT, uimm16nonzero, Select_GPR_Using_CC_Uimm16NonZero>;
1434-
def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPR_Using_CC_Uimm16NonZero>;
1412+
def : SelectQCbi<SETEQ, simm5nonzero, Select_GPR_Using_CC_SImm5NonZero>;
1413+
def : SelectQCbi<SETNE, simm5nonzero, Select_GPR_Using_CC_SImm5NonZero>;
1414+
def : SelectQCbi<SETLT, simm5nonzero, Select_GPR_Using_CC_SImm5NonZero>;
1415+
def : SelectQCbi<SETGE, simm5nonzero, Select_GPR_Using_CC_SImm5NonZero>;
1416+
def : SelectQCbi<SETULT, uimm5nonzero, Select_GPR_Using_CC_UImm5NonZero>;
1417+
def : SelectQCbi<SETUGE, uimm5nonzero, Select_GPR_Using_CC_UImm5NonZero>;
1418+
1419+
def : SelectQCbi<SETEQ, simm16nonzero, Select_GPR_Using_CC_SImm16NonZero>;
1420+
def : SelectQCbi<SETNE, simm16nonzero, Select_GPR_Using_CC_SImm16NonZero>;
1421+
def : SelectQCbi<SETLT, simm16nonzero, Select_GPR_Using_CC_SImm16NonZero>;
1422+
def : SelectQCbi<SETGE, simm16nonzero, Select_GPR_Using_CC_SImm16NonZero>;
1423+
def : SelectQCbi<SETULT, uimm16nonzero, Select_GPR_Using_CC_UImm16NonZero>;
1424+
def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPR_Using_CC_UImm16NonZero>;
14351425
} // let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2
14361426

14371427
let Predicates = [HasVendorXqcibm, IsRV32] in {

‎llvm/lib/Target/RISCV/RISCVInstrPredicates.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ def isSelectPseudo
4949
MCReturnStatement<
5050
CheckOpcode<[
5151
Select_GPR_Using_CC_GPR,
52-
Select_GPR_Using_CC_Imm,
52+
Select_GPR_Using_CC_SImm5,
5353
Select_FPR16_Using_CC_GPR,
5454
Select_FPR16INX_Using_CC_GPR,
5555
Select_FPR32_Using_CC_GPR,

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