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tangaactangaac
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add lasx support
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4 files changed

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‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1614,6 +1614,10 @@ static SDValue lower256BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
16141614
SmallVector<int> NewMask(Mask);
16151615
canonicalizeShuffleVectorByLane(DL, NewMask, VT, V1, V2, DAG);
16161616

1617+
APInt KnownUndef, KnownZero;
1618+
computeZeroableShuffleElements(NewMask, V1, V2, KnownUndef, KnownZero);
1619+
APInt Zeroable = KnownUndef | KnownZero;
1620+
16171621
SDValue Result;
16181622
// TODO: Add more comparison patterns.
16191623
if (V2.isUndef()) {
@@ -1641,6 +1645,9 @@ static SDValue lower256BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
16411645
return Result;
16421646
if ((Result = lowerVECTOR_SHUFFLE_XVPICKOD(DL, NewMask, VT, V1, V2, DAG)))
16431647
return Result;
1648+
if ((Result =
1649+
lowerVECTOR_SHUFFLEAsShift(DL, NewMask, VT, V1, V2, DAG, Zeroable)))
1650+
return Result;
16441651
if ((Result = lowerVECTOR_SHUFFLE_XVSHUF(DL, NewMask, VT, V1, V2, DAG)))
16451652
return Result;
16461653

‎llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td

Lines changed: 27 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1187,7 +1187,7 @@ multiclass PatShiftXrXr<SDPatternOperator OpNode, string Inst> {
11871187
(!cast<LAInst>(Inst#"_D") LASX256:$xj, LASX256:$xk)>;
11881188
}
11891189

1190-
multiclass PatShiftXrUimm<SDPatternOperator OpNode, string Inst> {
1190+
multiclass PatShiftXrSplatUimm<SDPatternOperator OpNode, string Inst> {
11911191
def : Pat<(OpNode (v32i8 LASX256:$xj), (v32i8 (SplatPat_uimm3 uimm3:$imm))),
11921192
(!cast<LAInst>(Inst#"_B") LASX256:$xj, uimm3:$imm)>;
11931193
def : Pat<(OpNode (v16i16 LASX256:$xj), (v16i16 (SplatPat_uimm4 uimm4:$imm))),
@@ -1198,6 +1198,17 @@ multiclass PatShiftXrUimm<SDPatternOperator OpNode, string Inst> {
11981198
(!cast<LAInst>(Inst#"_D") LASX256:$xj, uimm6:$imm)>;
11991199
}
12001200

1201+
multiclass PatShiftXrUimm<SDPatternOperator OpNode, string Inst> {
1202+
def : Pat<(OpNode(v32i8 LASX256:$vj), uimm3:$imm),
1203+
(!cast<LAInst>(Inst#"_B") LASX256:$vj, uimm3:$imm)>;
1204+
def : Pat<(OpNode(v16i16 LASX256:$vj), uimm4:$imm),
1205+
(!cast<LAInst>(Inst#"_H") LASX256:$vj, uimm4:$imm)>;
1206+
def : Pat<(OpNode(v8i32 LASX256:$vj), uimm5:$imm),
1207+
(!cast<LAInst>(Inst#"_W") LASX256:$vj, uimm5:$imm)>;
1208+
def : Pat<(OpNode(v4i64 LASX256:$vj), uimm6:$imm),
1209+
(!cast<LAInst>(Inst#"_D") LASX256:$vj, uimm6:$imm)>;
1210+
}
1211+
12011212
multiclass PatCCXrSimm5<CondCode CC, string Inst> {
12021213
def : Pat<(v32i8 (setcc (v32i8 LASX256:$xj),
12031214
(v32i8 (SplatPat_simm5 simm5:$imm)), CC)),
@@ -1335,20 +1346,32 @@ def : Pat<(or (v32i8 LASX256:$xj), (v32i8 (SplatPat_uimm8 uimm8:$imm))),
13351346
def : Pat<(xor (v32i8 LASX256:$xj), (v32i8 (SplatPat_uimm8 uimm8:$imm))),
13361347
(XVXORI_B LASX256:$xj, uimm8:$imm)>;
13371348

1349+
// XVBSLL_V
1350+
foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32,
1351+
v4f64] in def : Pat<(loongarch_vbsll(vt LASX256:$xj), uimm5:$imm),
1352+
(XVBSLL_V LASX256:$xj, uimm5:$imm)>;
1353+
1354+
// XVBSRL_V
1355+
foreach vt = [v32i8, v16i16, v8i32, v4i64, v8f32,
1356+
v4f64] in def : Pat<(loongarch_vbsrl(vt LASX256:$xj), uimm5:$imm),
1357+
(XVBSRL_V LASX256:$xj, uimm5:$imm)>;
1358+
13381359
// XVSLL[I]_{B/H/W/D}
13391360
defm : PatXrXr<shl, "XVSLL">;
13401361
defm : PatShiftXrXr<shl, "XVSLL">;
1341-
defm : PatShiftXrUimm<shl, "XVSLLI">;
1362+
defm : PatShiftXrSplatUimm<shl, "XVSLLI">;
1363+
defm : PatShiftXrUimm<loongarch_vslli, "XVSLLI">;
13421364

13431365
// XVSRL[I]_{B/H/W/D}
13441366
defm : PatXrXr<srl, "XVSRL">;
13451367
defm : PatShiftXrXr<srl, "XVSRL">;
1346-
defm : PatShiftXrUimm<srl, "XVSRLI">;
1368+
defm : PatShiftXrSplatUimm<srl, "XVSRLI">;
1369+
defm : PatShiftXrUimm<loongarch_vsrli, "XVSRLI">;
13471370

13481371
// XVSRA[I]_{B/H/W/D}
13491372
defm : PatXrXr<sra, "XVSRA">;
13501373
defm : PatShiftXrXr<sra, "XVSRA">;
1351-
defm : PatShiftXrUimm<sra, "XVSRAI">;
1374+
defm : PatShiftXrSplatUimm<sra, "XVSRAI">;
13521375

13531376
// XVCLZ_{B/H/W/D}
13541377
defm : PatXr<ctlz, "XVCLZ">;

‎llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-bit-shift.ll

Lines changed: 200 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,200 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3+
4+
define <32 x i8> @shuffle_to_xvslli_h_8(<32 x i8> %a) nounwind {
5+
; CHECK-LABEL: shuffle_to_xvslli_h_8:
6+
; CHECK: # %bb.0:
7+
; CHECK-NEXT: xvslli.h $xr0, $xr0, 8
8+
; CHECK-NEXT: ret
9+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 0, i32 32, i32 2, i32 32, i32 4, i32 32, i32 6, i32 32, i32 8, i32 32, i32 10, i32 32, i32 12, i32 32, i32 14, i32 32, i32 16, i32 32, i32 18, i32 32, i32 20, i32 32, i32 22, i32 32, i32 24, i32 32, i32 26, i32 32, i32 28, i32 32, i32 30>
10+
ret <32 x i8> %shuffle
11+
}
12+
13+
define <32 x i8> @shuffle_to_xvsrli_h_8(<32 x i8> %a) nounwind {
14+
; CHECK-LABEL: shuffle_to_xvsrli_h_8:
15+
; CHECK: # %bb.0:
16+
; CHECK-NEXT: xvsrli.h $xr0, $xr0, 8
17+
; CHECK-NEXT: ret
18+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 1, i32 32, i32 3, i32 32, i32 5, i32 32, i32 7, i32 32, i32 9, i32 32, i32 11, i32 32, i32 13, i32 32, i32 15, i32 32, i32 17, i32 32, i32 19, i32 32, i32 21, i32 32, i32 23, i32 32, i32 25, i32 32, i32 27, i32 32, i32 29, i32 32, i32 31, i32 32>
19+
ret <32 x i8> %shuffle
20+
}
21+
22+
define <32 x i8> @shuffle_to_xvslli_w_8(<32 x i8> %a) nounwind {
23+
; CHECK-LABEL: shuffle_to_xvslli_w_8:
24+
; CHECK: # %bb.0:
25+
; CHECK-NEXT: xvslli.w $xr0, $xr0, 8
26+
; CHECK-NEXT: ret
27+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 0, i32 1, i32 2, i32 32, i32 4, i32 5, i32 6, i32 32, i32 8, i32 9, i32 10, i32 32, i32 12, i32 13, i32 14, i32 32, i32 16, i32 17, i32 18, i32 32, i32 20, i32 21, i32 22, i32 32, i32 24, i32 25, i32 26, i32 32, i32 28, i32 29, i32 30>
28+
ret <32 x i8> %shuffle
29+
}
30+
31+
define <32 x i8> @shuffle_to_xvsrli_w_8(<32 x i8> %a) nounwind {
32+
; CHECK-LABEL: shuffle_to_xvsrli_w_8:
33+
; CHECK: # %bb.0:
34+
; CHECK-NEXT: xvsrli.w $xr0, $xr0, 8
35+
; CHECK-NEXT: ret
36+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 1, i32 2, i32 3, i32 32, i32 5, i32 6, i32 7, i32 32, i32 9, i32 10, i32 11, i32 32, i32 13, i32 14, i32 15, i32 32, i32 17, i32 18, i32 19, i32 32, i32 21, i32 22, i32 23, i32 32, i32 25, i32 26, i32 27, i32 32, i32 29, i32 30, i32 31, i32 32>
37+
ret <32 x i8> %shuffle
38+
}
39+
40+
define <16 x i16> @shuffle_to_xvslli_w_16(<16 x i16> %a) nounwind {
41+
; CHECK-LABEL: shuffle_to_xvslli_w_16:
42+
; CHECK: # %bb.0:
43+
; CHECK-NEXT: xvslli.w $xr0, $xr0, 16
44+
; CHECK-NEXT: ret
45+
%shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 16, i32 0, i32 16, i32 2, i32 16, i32 4, i32 16, i32 6, i32 16, i32 8, i32 16, i32 10, i32 16, i32 12, i32 16, i32 14>
46+
ret <16 x i16> %shuffle
47+
}
48+
49+
define <16 x i16> @shuffle_to_xvsrli_w_16(<16 x i16> %a) nounwind {
50+
; CHECK-LABEL: shuffle_to_xvsrli_w_16:
51+
; CHECK: # %bb.0:
52+
; CHECK-NEXT: xvsrli.w $xr0, $xr0, 16
53+
; CHECK-NEXT: ret
54+
%shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 1, i32 16, i32 3, i32 16, i32 5, i32 16, i32 7, i32 16, i32 9, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15, i32 16>
55+
ret <16 x i16> %shuffle
56+
}
57+
58+
define <32 x i8> @shuffle_to_xvslli_w_24(<32 x i8> %a) nounwind {
59+
; CHECK-LABEL: shuffle_to_xvslli_w_24:
60+
; CHECK: # %bb.0:
61+
; CHECK-NEXT: xvslli.w $xr0, $xr0, 24
62+
; CHECK-NEXT: ret
63+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 32, i32 32, i32 0, i32 32, i32 32, i32 32, i32 4, i32 32, i32 32, i32 32, i32 8, i32 32, i32 32, i32 32, i32 12, i32 32, i32 32, i32 32, i32 16, i32 32, i32 32, i32 32, i32 20, i32 32, i32 32, i32 32, i32 24, i32 32, i32 32, i32 32, i32 28>
64+
ret <32 x i8> %shuffle
65+
}
66+
67+
define <32 x i8> @shuffle_to_xvsrli_w_24(<32 x i8> %a) nounwind {
68+
; CHECK-LABEL: shuffle_to_xvsrli_w_24:
69+
; CHECK: # %bb.0:
70+
; CHECK-NEXT: xvsrli.w $xr0, $xr0, 24
71+
; CHECK-NEXT: ret
72+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 3, i32 32, i32 32, i32 32, i32 7, i32 32, i32 32, i32 32, i32 11, i32 32, i32 32, i32 32, i32 15, i32 32, i32 32, i32 32, i32 19, i32 32, i32 32, i32 32, i32 23, i32 32, i32 32, i32 32, i32 27, i32 32, i32 32, i32 32, i32 31, i32 32, i32 32, i32 32>
73+
ret <32 x i8> %shuffle
74+
}
75+
76+
define <32 x i8> @shuffle_to_xvslli_d_8(<32 x i8> %a) nounwind {
77+
; CHECK-LABEL: shuffle_to_xvslli_d_8:
78+
; CHECK: # %bb.0:
79+
; CHECK-NEXT: xvslli.d $xr0, $xr0, 8
80+
; CHECK-NEXT: ret
81+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 32, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 32, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 32, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30>
82+
ret <32 x i8> %shuffle
83+
}
84+
85+
define <32 x i8> @shuffle_to_xvsrli_d_8(<32 x i8> %a) nounwind {
86+
; CHECK-LABEL: shuffle_to_xvsrli_d_8:
87+
; CHECK: # %bb.0:
88+
; CHECK-NEXT: xvsrli.d $xr0, $xr0, 8
89+
; CHECK-NEXT: ret
90+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 32, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 32, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32>
91+
ret <32 x i8> %shuffle
92+
}
93+
94+
define <16 x i16> @shuffle_to_xvslli_d_16(<16 x i16> %a) nounwind {
95+
; CHECK-LABEL: shuffle_to_xvslli_d_16:
96+
; CHECK: # %bb.0:
97+
; CHECK-NEXT: xvslli.d $xr0, $xr0, 16
98+
; CHECK-NEXT: ret
99+
%shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 16, i32 0, i32 1, i32 2, i32 16, i32 4, i32 5, i32 6, i32 16, i32 8, i32 9, i32 10, i32 16, i32 12, i32 13, i32 14>
100+
ret <16 x i16> %shuffle
101+
}
102+
103+
define <16 x i16> @shuffle_to_xvsrli_d_16(<16 x i16> %a) nounwind {
104+
; CHECK-LABEL: shuffle_to_xvsrli_d_16:
105+
; CHECK: # %bb.0:
106+
; CHECK-NEXT: xvsrli.d $xr0, $xr0, 16
107+
; CHECK-NEXT: ret
108+
%shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 1, i32 2, i32 3, i32 16, i32 5, i32 6, i32 7, i32 16, i32 9, i32 10, i32 11, i32 16, i32 13, i32 14, i32 15, i32 16>
109+
ret <16 x i16> %shuffle
110+
}
111+
112+
define <32 x i8> @shuffle_to_xvslli_d_24(<32 x i8> %a) nounwind {
113+
; CHECK-LABEL: shuffle_to_xvslli_d_24:
114+
; CHECK: # %bb.0:
115+
; CHECK-NEXT: xvslli.d $xr0, $xr0, 24
116+
; CHECK-NEXT: ret
117+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 32, i32 32, i32 0, i32 1, i32 2, i32 3, i32 4, i32 32, i32 32, i32 32, i32 8, i32 9, i32 10, i32 11, i32 12, i32 32, i32 32, i32 32, i32 16, i32 17, i32 18, i32 19, i32 20, i32 32, i32 32, i32 32, i32 24, i32 25, i32 26, i32 27, i32 28>
118+
ret <32 x i8> %shuffle
119+
}
120+
121+
define <32 x i8> @shuffle_to_xvsrli_d_24(<32 x i8> %a) nounwind {
122+
; CHECK-LABEL: shuffle_to_xvsrli_d_24:
123+
; CHECK: # %bb.0:
124+
; CHECK-NEXT: xvsrli.d $xr0, $xr0, 24
125+
; CHECK-NEXT: ret
126+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 32, i32 32, i32 32, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 32, i32 32, i32 19, i32 20, i32 21, i32 22, i32 23, i32 32, i32 32, i32 32, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 32, i32 32>
127+
ret <32 x i8> %shuffle
128+
}
129+
130+
define <8 x i32> @shuffle_to_xvslli_d_32(<8 x i32> %a) nounwind {
131+
; CHECK-LABEL: shuffle_to_xvslli_d_32:
132+
; CHECK: # %bb.0:
133+
; CHECK-NEXT: xvslli.d $xr0, $xr0, 32
134+
; CHECK-NEXT: ret
135+
%shuffle = shufflevector <8 x i32> %a, <8 x i32> zeroinitializer, <8 x i32> <i32 8, i32 0, i32 8, i32 2, i32 8, i32 4, i32 8, i32 6>
136+
ret <8 x i32> %shuffle
137+
}
138+
139+
define <8 x i32> @shuffle_to_xvsrli_d_32(<8 x i32> %a) nounwind {
140+
; CHECK-LABEL: shuffle_to_xvsrli_d_32:
141+
; CHECK: # %bb.0:
142+
; CHECK-NEXT: xvsrli.d $xr0, $xr0, 32
143+
; CHECK-NEXT: ret
144+
%shuffle = shufflevector <8 x i32> %a, <8 x i32> zeroinitializer, <8 x i32> <i32 1, i32 8, i32 3, i32 8, i32 5, i32 8, i32 7, i32 8>
145+
ret <8 x i32> %shuffle
146+
}
147+
148+
define <32 x i8> @shuffle_to_xvslli_d_40(<32 x i8> %a) nounwind {
149+
; CHECK-LABEL: shuffle_to_xvslli_d_40:
150+
; CHECK: # %bb.0:
151+
; CHECK-NEXT: xvslli.d $xr0, $xr0, 40
152+
; CHECK-NEXT: ret
153+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 0, i32 1, i32 2, i32 32, i32 32, i32 32, i32 32, i32 32, i32 8, i32 9, i32 10, i32 32, i32 32, i32 32, i32 32, i32 32, i32 16, i32 17, i32 18, i32 32, i32 32, i32 32, i32 32, i32 32, i32 24, i32 25, i32 26>
154+
ret <32 x i8> %shuffle
155+
}
156+
157+
define <32 x i8> @shuffle_to_xvsrli_d_40(<32 x i8> %a) nounwind {
158+
; CHECK-LABEL: shuffle_to_xvsrli_d_40:
159+
; CHECK: # %bb.0:
160+
; CHECK-NEXT: xvsrli.d $xr0, $xr0, 40
161+
; CHECK-NEXT: ret
162+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 5, i32 6, i32 7, i32 32, i32 32, i32 32, i32 32, i32 32, i32 13, i32 14, i32 15, i32 32, i32 32, i32 32, i32 32, i32 32, i32 21, i32 22, i32 23, i32 32, i32 32, i32 32, i32 32, i32 32, i32 29, i32 30, i32 31, i32 32, i32 32, i32 32, i32 32, i32 32>
163+
ret <32 x i8> %shuffle
164+
}
165+
166+
define <16 x i16> @shuffle_to_xvslli_d_48(<16 x i16> %a) nounwind {
167+
; CHECK-LABEL: shuffle_to_xvslli_d_48:
168+
; CHECK: # %bb.0:
169+
; CHECK-NEXT: xvslli.d $xr0, $xr0, 48
170+
; CHECK-NEXT: ret
171+
%shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 16, i32 16, i32 16, i32 0, i32 16, i32 16, i32 16, i32 4, i32 16, i32 16, i32 16, i32 8, i32 16, i32 16, i32 16, i32 12>
172+
ret <16 x i16> %shuffle
173+
}
174+
175+
define <16 x i16> @shuffle_to_xvsrli_d_48(<16 x i16> %a) nounwind {
176+
; CHECK-LABEL: shuffle_to_xvsrli_d_48:
177+
; CHECK: # %bb.0:
178+
; CHECK-NEXT: xvsrli.d $xr0, $xr0, 48
179+
; CHECK-NEXT: ret
180+
%shuffle = shufflevector <16 x i16> %a, <16 x i16> zeroinitializer, <16 x i32> <i32 3, i32 16, i32 16, i32 16, i32 7, i32 16, i32 16, i32 16, i32 11, i32 16, i32 16, i32 16, i32 15, i32 16, i32 16, i32 16>
181+
ret <16 x i16> %shuffle
182+
}
183+
184+
define <32 x i8> @shuffle_to_xvslli_d_56(<32 x i8> %a) nounwind {
185+
; CHECK-LABEL: shuffle_to_xvslli_d_56:
186+
; CHECK: # %bb.0:
187+
; CHECK-NEXT: xvslli.d $xr0, $xr0, 56
188+
; CHECK-NEXT: ret
189+
%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 0, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 8, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 16, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 24>
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ret <32 x i8> %shuffle
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}
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define <32 x i8> @shuffle_to_xvsrli_d_56(<32 x i8> %a) nounwind {
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; CHECK-LABEL: shuffle_to_xvsrli_d_56:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xvsrli.d $xr0, $xr0, 56
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; CHECK-NEXT: ret
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%shuffle = shufflevector <32 x i8> %a, <32 x i8> zeroinitializer, <32 x i32> <i32 7, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 15, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 23, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 31, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
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ret <32 x i8> %shuffle
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}

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