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[AARCH64] Add support for Cortex-A320 (#139055)
This patch adds initial support for the recently announced Armv9 Cortex-A320 processor. For more information, including the Technical Reference Manual, see: https://developer.arm.com/Processors/Cortex-A320 --------- Co-authored-by: Oliver Stannard <[email protected]>
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‎clang/docs/ReleaseNotes.rst

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@@ -728,6 +728,9 @@ X86 Support
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Arm and AArch64 Support
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^^^^^^^^^^^^^^^^^^^^^^^
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- Support has been added for the following processors (command-line identifiers in parentheses):
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- Arm Cortex-A320 (``cortex-a320``)
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- For ARM targets, cc1as now considers the FPU's features for the selected CPU or Architecture.
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- The ``+nosimd`` attribute is now fully supported for ARM. Previously, this had no effect when being used with
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ARM targets, however this will now disable NEON instructions being generated. The ``simd`` option is

‎clang/test/Driver/aarch64-cortex-a320.c

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// RUN: not %clang --target=arm-arm-none-eabi -mcpu=cortex-a320 %s 2>&1 | FileCheck %s
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// CHECK: error: unsupported argument {{.*}} to option '-mcpu='
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// RUN: %clang -target aarch64 -mcpu=cortex-a320 -### -c %s 2>&1 | FileCheck -check-prefix=A320 %s
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// A320: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a320"
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‎clang/test/Driver/print-enabled-extensions/aarch64-cortex-a320.c

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// REQUIRES: aarch64-registered-target
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// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=cortex-a320 | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
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// CHECK: Extensions enabled for the given AArch64 target
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// CHECK-EMPTY:
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// CHECK-NEXT: Architecture Feature(s) Description
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// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension
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// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support
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// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions
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// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension
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// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification
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// CHECK-NEXT: FEAT_CCIDX Enable Armv8.3-A Extend of the CCSIDR number of sets
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// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions
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// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction
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// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions
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// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence
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// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence
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// CHECK-NEXT: FEAT_DotProd Enable dot product support
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// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension
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// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension
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// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support
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// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension
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// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions
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// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions
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// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing
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// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int
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// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions
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// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons
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// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register
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// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension
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// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions
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// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension
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// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension
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// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets
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// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions
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// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules
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// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension
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// CHECK-NEXT: FEAT_MTE, FEAT_MTE2 Enable Memory Tagging Extension
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// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement
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// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension
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// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants
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// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension
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// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension
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// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions
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// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions
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// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
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// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions
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// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions
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// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
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// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension
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// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
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// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState
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// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension
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// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction
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// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction
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‎clang/test/Misc/target-invalid-cpu-note/aarch64.c

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// CHECK-SAME: {{^}}, apple-s9
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// CHECK-SAME: {{^}}, carmel
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// CHECK-SAME: {{^}}, cobalt-100
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// CHECK-SAME: {{^}}, cortex-a320
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// CHECK-SAME: {{^}}, cortex-a34
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// CHECK-SAME: {{^}}, cortex-a35
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// CHECK-SAME: {{^}}, cortex-a510

‎llvm/lib/Target/AArch64/AArch64Processors.td

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def TuneA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
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"Cortex-A35 ARM processors">;
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def TuneA320 : SubtargetFeature<"a320", "ARMProcFamily", "CortexA320",
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"Cortex-A320 ARM processors", [
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FeatureFuseAES,
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FeatureFuseAdrpAdd,
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FeaturePostRAScheduler]>;
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def TuneA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
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"Cortex-A53 ARM processors", [
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FeatureFuseAES,
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HasV8_6aOps]>;
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def ProcessorFeatures {
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list<SubtargetFeature> A320 = [HasV9_2aOps, FeatureNEON, FeatureMTE,
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FeatureSVEBitPerm, FeatureFP16FML, FeatureFullFP16,
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FeatureETE, FeaturePerfMon, FeatureCCIDX,
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FeatureCCPP, FeatureComplxNum, FeatureCRC,
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FeatureDotProd, FeatureJS, FeatureLOR,
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FeatureLSE, FeaturePAN, FeaturePAN_RWV,
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FeaturePAuth, FeaturePsUAO, FeatureRAS,
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FeatureRDM, FeatureTRBE, FeatureVH,
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FeatureFlagM, FeaturePredRes, FeatureSB, FeatureSSBS,
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FeatureSVE, FeatureSVE2];
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list<SubtargetFeature> A53 = [HasV8_0aOps, FeatureCRC, FeatureSHA2, FeatureAES,
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FeatureFPARMv8, FeatureNEON, FeaturePerfMon];
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list<SubtargetFeature> A55 = [HasV8_2aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8,
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def : ProcessorModel<"generic", CortexA510Model, ProcessorFeatures.Generic,
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[FeatureFuseAES, FeatureFuseAdrpAdd, FeaturePostRAScheduler,
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FeatureEnableSelectOptimize]>;
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def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,
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[TuneA35]>;
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def : ProcessorModel<"cortex-a34", CortexA53Model, ProcessorFeatures.A53,
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[TuneA35]>;
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def : ProcessorModel<"cortex-a35", CortexA53Model, ProcessorFeatures.A53,
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[TuneA35]>;
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def : ProcessorModel<"cortex-a320", CortexA510Model, ProcessorFeatures.A320,
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[TuneA320]>;
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def : ProcessorModel<"cortex-a53", CortexA53Model, ProcessorFeatures.A53,
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[TuneA53]>;
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def : ProcessorModel<"cortex-a55", CortexA55Model, ProcessorFeatures.A55,

‎llvm/lib/Target/AArch64/AArch64Subtarget.cpp

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PrefLoopAlignment = Align(32);
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MaxBytesForLoopAlignment = 16;
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break;
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case CortexA320:
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case CortexA510:
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case CortexA520:
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PrefFunctionAlignment = Align(16);

‎llvm/lib/TargetParser/Host.cpp

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@@ -228,6 +228,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
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.Case("0xd14", "cortex-r82ae")
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.Case("0xd02", "cortex-a34")
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.Case("0xd04", "cortex-a35")
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.Case("0xd8f", "cortex-a320")
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.Case("0xd03", "cortex-a53")
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.Case("0xd05", "cortex-a55")
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.Case("0xd46", "cortex-a510")

‎llvm/unittests/TargetParser/Host.cpp

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}
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TEST(getLinuxHostCPUName, AArch64) {
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
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"CPU part : 0xd8f"),
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"cortex-a320");
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EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x41\n"
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"CPU part : 0xd03"),
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"cortex-a53");

‎llvm/unittests/TargetParser/TargetParserTest.cpp

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@@ -1085,6 +1085,7 @@ INSTANTIATE_TEST_SUITE_P(
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AArch64CPUTests, AArch64CPUTestFixture,
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::testing::Values(AArch64CPUTestParams("cortex-a34", "armv8-a"),
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AArch64CPUTestParams("cortex-a35", "armv8-a"),
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AArch64CPUTestParams("cortex-a320", "armv9.2-a"),
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AArch64CPUTestParams("cortex-a53", "armv8-a"),
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AArch64CPUTestParams("cortex-a55", "armv8.2-a"),
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AArch64CPUTestParams("cortex-a510", "armv9-a"),
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AArch64CPUAliasTestParams::PrintToStringParamName);
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// Note: number of CPUs includes aliases.
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static constexpr unsigned NumAArch64CPUArchs = 89;
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static constexpr unsigned NumAArch64CPUArchs = 90;
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TEST(TargetParserTest, testAArch64CPUArchList) {
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SmallVector<StringRef, NumAArch64CPUArchs> List;

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