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[RISCV] Don't prefer QC_EXT for SEXT_INREG patterns when Zbb is enabled (#144837)
`Zbb` has the `sext.b` and `sext.h` instructions that are compressible.
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‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1439,8 +1439,6 @@ def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC
14391439
} // let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2
14401440

14411441
let Predicates = [HasVendorXqcibm, IsRV32] in {
1442-
def : Pat<(sext_inreg (i32 GPR:$rs1), i16), (QC_EXT GPR:$rs1, 16, 0)>;
1443-
def : Pat<(sext_inreg (i32 GPR:$rs1), i8), (QC_EXT GPR:$rs1, 8, 0)>;
14441442
def : Pat<(sext_inreg (i32 GPR:$rs1), i1), (QC_EXT GPR:$rs1, 1, 0)>;
14451443

14461444
// Prefer qc.extu to andi for the following cases since the former can be compressed
@@ -1452,6 +1450,12 @@ def : Pat<(i32 (and GPRNoX0:$rs, 1023)), (QC_EXTU GPRNoX0:$rs, 10, 0)>;
14521450
def : Pat<(i32 (and GPRNoX0:$rs, 2047)), (QC_EXTU GPRNoX0:$rs, 11, 0)>;
14531451
} // Predicates = [HasVendorXqcibm, IsRV32]
14541452

1453+
// If Zbb is enabled sext.b/h is preferred since they are compressible
1454+
let Predicates = [HasVendorXqcibm, NoStdExtZbb, IsRV32] in {
1455+
def : Pat<(sext_inreg (i32 GPR:$rs1), i16), (QC_EXT GPR:$rs1, 16, 0)>;
1456+
def : Pat<(sext_inreg (i32 GPR:$rs1), i8), (QC_EXT GPR:$rs1, 8, 0)>;
1457+
} // Predicates = [HasVendorXqcibm, NoStdExtZbb, IsRV32]
1458+
14551459
let Predicates = [HasVendorXqcibm, HasStdExtZbb, IsRV32] in {
14561460
def: Pat<(i32 (cttz (not (i32 GPR:$rs1)))), (QC_CTO GPR:$rs1)>;
14571461
def: Pat<(i32 (ctlz (not (i32 GPR:$rs1)))), (QC_CLO GPR:$rs1)>;

‎llvm/test/CodeGen/RISCV/xqcibm-extract.ll

Lines changed: 141 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,8 @@
33
; RUN: | FileCheck %s -check-prefixes=RV32I
44
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm -verify-machineinstrs < %s \
55
; RUN: | FileCheck %s -check-prefixes=RV32XQCIBM
6+
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm,+zbb -verify-machineinstrs < %s \
7+
; RUN: | FileCheck %s -check-prefixes=RV32XQCIBMZBB
68

79
define i32 @sexti1_i32(i1 %a) nounwind {
810
; RV32I-LABEL: sexti1_i32:
@@ -15,6 +17,11 @@ define i32 @sexti1_i32(i1 %a) nounwind {
1517
; RV32XQCIBM: # %bb.0:
1618
; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0
1719
; RV32XQCIBM-NEXT: ret
20+
;
21+
; RV32XQCIBMZBB-LABEL: sexti1_i32:
22+
; RV32XQCIBMZBB: # %bb.0:
23+
; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 0
24+
; RV32XQCIBMZBB-NEXT: ret
1825
%sext = sext i1 %a to i32
1926
ret i32 %sext
2027
}
@@ -30,6 +37,11 @@ define i32 @sexti1_i32_2(i32 %a) {
3037
; RV32XQCIBM: # %bb.0:
3138
; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0
3239
; RV32XQCIBM-NEXT: ret
40+
;
41+
; RV32XQCIBMZBB-LABEL: sexti1_i32_2:
42+
; RV32XQCIBMZBB: # %bb.0:
43+
; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 0
44+
; RV32XQCIBMZBB-NEXT: ret
3345
%shl = shl i32 %a, 31
3446
%shr = ashr exact i32 %shl, 31
3547
ret i32 %shr
@@ -47,6 +59,11 @@ define i32 @sexti8_i32(i8 %a) nounwind {
4759
; RV32XQCIBM: # %bb.0:
4860
; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 0
4961
; RV32XQCIBM-NEXT: ret
62+
;
63+
; RV32XQCIBMZBB-LABEL: sexti8_i32:
64+
; RV32XQCIBMZBB: # %bb.0:
65+
; RV32XQCIBMZBB-NEXT: sext.b a0, a0
66+
; RV32XQCIBMZBB-NEXT: ret
5067
%sext = sext i8 %a to i32
5168
ret i32 %sext
5269
}
@@ -62,6 +79,11 @@ define i32 @sexti8_i32_2(i32 %a) {
6279
; RV32XQCIBM: # %bb.0:
6380
; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 0
6481
; RV32XQCIBM-NEXT: ret
82+
;
83+
; RV32XQCIBMZBB-LABEL: sexti8_i32_2:
84+
; RV32XQCIBMZBB: # %bb.0:
85+
; RV32XQCIBMZBB-NEXT: sext.b a0, a0
86+
; RV32XQCIBMZBB-NEXT: ret
6587
%shl = shl i32 %a, 24
6688
%shr = ashr exact i32 %shl, 24
6789
ret i32 %shr
@@ -78,6 +100,11 @@ define i32 @sexti16_i32(i16 %a) nounwind {
78100
; RV32XQCIBM: # %bb.0:
79101
; RV32XQCIBM-NEXT: qc.ext a0, a0, 16, 0
80102
; RV32XQCIBM-NEXT: ret
103+
;
104+
; RV32XQCIBMZBB-LABEL: sexti16_i32:
105+
; RV32XQCIBMZBB: # %bb.0:
106+
; RV32XQCIBMZBB-NEXT: sext.h a0, a0
107+
; RV32XQCIBMZBB-NEXT: ret
81108
%sext = sext i16 %a to i32
82109
ret i32 %sext
83110
}
@@ -93,6 +120,11 @@ define i32 @sexti16_i32_2(i32 %a) {
93120
; RV32XQCIBM: # %bb.0:
94121
; RV32XQCIBM-NEXT: qc.ext a0, a0, 16, 0
95122
; RV32XQCIBM-NEXT: ret
123+
;
124+
; RV32XQCIBMZBB-LABEL: sexti16_i32_2:
125+
; RV32XQCIBMZBB: # %bb.0:
126+
; RV32XQCIBMZBB-NEXT: sext.h a0, a0
127+
; RV32XQCIBMZBB-NEXT: ret
96128
%shl = shl i32 %a, 16
97129
%shr = ashr exact i32 %shl, 16
98130
ret i32 %shr
@@ -111,6 +143,12 @@ define i64 @sexti1_i64(i64 %a) {
111143
; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0
112144
; RV32XQCIBM-NEXT: mv a1, a0
113145
; RV32XQCIBM-NEXT: ret
146+
;
147+
; RV32XQCIBMZBB-LABEL: sexti1_i64:
148+
; RV32XQCIBMZBB: # %bb.0:
149+
; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 0
150+
; RV32XQCIBMZBB-NEXT: mv a1, a0
151+
; RV32XQCIBMZBB-NEXT: ret
114152
%shl = shl i64 %a, 63
115153
%shr = ashr exact i64 %shl, 63
116154
ret i64 %shr
@@ -129,6 +167,12 @@ define i64 @sexti1_i64_2(i1 %a) {
129167
; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 0
130168
; RV32XQCIBM-NEXT: mv a1, a0
131169
; RV32XQCIBM-NEXT: ret
170+
;
171+
; RV32XQCIBMZBB-LABEL: sexti1_i64_2:
172+
; RV32XQCIBMZBB: # %bb.0:
173+
; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 0
174+
; RV32XQCIBMZBB-NEXT: mv a1, a0
175+
; RV32XQCIBMZBB-NEXT: ret
132176
%1 = sext i1 %a to i64
133177
ret i64 %1
134178
}
@@ -146,6 +190,12 @@ define i64 @sexti8_i64(i64 %a) {
146190
; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 0
147191
; RV32XQCIBM-NEXT: srai a1, a0, 31
148192
; RV32XQCIBM-NEXT: ret
193+
;
194+
; RV32XQCIBMZBB-LABEL: sexti8_i64:
195+
; RV32XQCIBMZBB: # %bb.0:
196+
; RV32XQCIBMZBB-NEXT: sext.b a0, a0
197+
; RV32XQCIBMZBB-NEXT: srai a1, a0, 31
198+
; RV32XQCIBMZBB-NEXT: ret
149199
%shl = shl i64 %a, 56
150200
%shr = ashr exact i64 %shl, 56
151201
ret i64 %shr
@@ -164,6 +214,12 @@ define i64 @sexti8_i64_2(i8 %a) {
164214
; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 0
165215
; RV32XQCIBM-NEXT: srai a1, a0, 31
166216
; RV32XQCIBM-NEXT: ret
217+
;
218+
; RV32XQCIBMZBB-LABEL: sexti8_i64_2:
219+
; RV32XQCIBMZBB: # %bb.0:
220+
; RV32XQCIBMZBB-NEXT: sext.b a0, a0
221+
; RV32XQCIBMZBB-NEXT: srai a1, a0, 31
222+
; RV32XQCIBMZBB-NEXT: ret
167223
%1 = sext i8 %a to i64
168224
ret i64 %1
169225
}
@@ -181,6 +237,12 @@ define i64 @sexti16_i64(i64 %a) {
181237
; RV32XQCIBM-NEXT: qc.ext a0, a0, 16, 0
182238
; RV32XQCIBM-NEXT: srai a1, a0, 31
183239
; RV32XQCIBM-NEXT: ret
240+
;
241+
; RV32XQCIBMZBB-LABEL: sexti16_i64:
242+
; RV32XQCIBMZBB: # %bb.0:
243+
; RV32XQCIBMZBB-NEXT: sext.h a0, a0
244+
; RV32XQCIBMZBB-NEXT: srai a1, a0, 31
245+
; RV32XQCIBMZBB-NEXT: ret
184246
%shl = shl i64 %a, 48
185247
%shr = ashr exact i64 %shl, 48
186248
ret i64 %shr
@@ -199,6 +261,12 @@ define i64 @sexti16_i64_2(i16 %a) {
199261
; RV32XQCIBM-NEXT: qc.ext a0, a0, 16, 0
200262
; RV32XQCIBM-NEXT: srai a1, a0, 31
201263
; RV32XQCIBM-NEXT: ret
264+
;
265+
; RV32XQCIBMZBB-LABEL: sexti16_i64_2:
266+
; RV32XQCIBMZBB: # %bb.0:
267+
; RV32XQCIBMZBB-NEXT: sext.h a0, a0
268+
; RV32XQCIBMZBB-NEXT: srai a1, a0, 31
269+
; RV32XQCIBMZBB-NEXT: ret
202270
%1 = sext i16 %a to i64
203271
ret i64 %1
204272
}
@@ -213,6 +281,11 @@ define i64 @sexti32_i64(i64 %a) {
213281
; RV32XQCIBM: # %bb.0:
214282
; RV32XQCIBM-NEXT: srai a1, a0, 31
215283
; RV32XQCIBM-NEXT: ret
284+
;
285+
; RV32XQCIBMZBB-LABEL: sexti32_i64:
286+
; RV32XQCIBMZBB: # %bb.0:
287+
; RV32XQCIBMZBB-NEXT: srai a1, a0, 31
288+
; RV32XQCIBMZBB-NEXT: ret
216289
%shl = shl i64 %a, 32
217290
%shr = ashr exact i64 %shl, 32
218291
ret i64 %shr
@@ -228,6 +301,11 @@ define i64 @sexti32_i64_2(i32 %a) {
228301
; RV32XQCIBM: # %bb.0:
229302
; RV32XQCIBM-NEXT: srai a1, a0, 31
230303
; RV32XQCIBM-NEXT: ret
304+
;
305+
; RV32XQCIBMZBB-LABEL: sexti32_i64_2:
306+
; RV32XQCIBMZBB: # %bb.0:
307+
; RV32XQCIBMZBB-NEXT: srai a1, a0, 31
308+
; RV32XQCIBMZBB-NEXT: ret
231309
%1 = sext i32 %a to i64
232310
ret i64 %1
233311
}
@@ -243,6 +321,11 @@ define i32 @extu_from_and_i32(i32 %x) {
243321
; RV32XQCIBM: # %bb.0:
244322
; RV32XQCIBM-NEXT: qc.extu a0, a0, 12, 0
245323
; RV32XQCIBM-NEXT: ret
324+
;
325+
; RV32XQCIBMZBB-LABEL: extu_from_and_i32:
326+
; RV32XQCIBMZBB: # %bb.0:
327+
; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 12, 0
328+
; RV32XQCIBMZBB-NEXT: ret
246329
%a = and i32 %x, 4095
247330
ret i32 %a
248331
}
@@ -257,6 +340,11 @@ define i32 @no_extu_from_and_i32(i32 %x) {
257340
; RV32XQCIBM: # %bb.0:
258341
; RV32XQCIBM-NEXT: andi a0, a0, 31
259342
; RV32XQCIBM-NEXT: ret
343+
;
344+
; RV32XQCIBMZBB-LABEL: no_extu_from_and_i32:
345+
; RV32XQCIBMZBB: # %bb.0:
346+
; RV32XQCIBMZBB-NEXT: andi a0, a0, 31
347+
; RV32XQCIBMZBB-NEXT: ret
260348
%a = and i32 %x, 31
261349
ret i32 %a
262350
}
@@ -271,6 +359,11 @@ define i32 @extu_from_and_i32_simm12_lb(i32 %x) {
271359
; RV32XQCIBM: # %bb.0:
272360
; RV32XQCIBM-NEXT: qc.extu a0, a0, 6, 0
273361
; RV32XQCIBM-NEXT: ret
362+
;
363+
; RV32XQCIBMZBB-LABEL: extu_from_and_i32_simm12_lb:
364+
; RV32XQCIBMZBB: # %bb.0:
365+
; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 6, 0
366+
; RV32XQCIBMZBB-NEXT: ret
274367
%a = and i32 %x, 63
275368
ret i32 %a
276369
}
@@ -285,6 +378,11 @@ define i32 @extu_from_and_i32_simm12_ub(i32 %x) {
285378
; RV32XQCIBM: # %bb.0:
286379
; RV32XQCIBM-NEXT: qc.extu a0, a0, 11, 0
287380
; RV32XQCIBM-NEXT: ret
381+
;
382+
; RV32XQCIBMZBB-LABEL: extu_from_and_i32_simm12_ub:
383+
; RV32XQCIBMZBB: # %bb.0:
384+
; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 11, 0
385+
; RV32XQCIBMZBB-NEXT: ret
288386
%a = and i32 %x, 2047
289387
ret i32 %a
290388
}
@@ -302,6 +400,12 @@ define i64 @extu_from_and_i64(i64 %x) {
302400
; RV32XQCIBM-NEXT: qc.extu a0, a0, 12, 0
303401
; RV32XQCIBM-NEXT: li a1, 0
304402
; RV32XQCIBM-NEXT: ret
403+
;
404+
; RV32XQCIBMZBB-LABEL: extu_from_and_i64:
405+
; RV32XQCIBMZBB: # %bb.0:
406+
; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 12, 0
407+
; RV32XQCIBMZBB-NEXT: li a1, 0
408+
; RV32XQCIBMZBB-NEXT: ret
305409
%a = and i64 %x, 4095
306410
ret i64 %a
307411
}
@@ -317,6 +421,11 @@ define i32 @extu_from_and_lshr_i32(i32 %x) {
317421
; RV32XQCIBM: # %bb.0:
318422
; RV32XQCIBM-NEXT: qc.extu a0, a0, 3, 23
319423
; RV32XQCIBM-NEXT: ret
424+
;
425+
; RV32XQCIBMZBB-LABEL: extu_from_and_lshr_i32:
426+
; RV32XQCIBMZBB: # %bb.0:
427+
; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 3, 23
428+
; RV32XQCIBMZBB-NEXT: ret
320429
%shifted = lshr i32 %x, 23
321430
%masked = and i32 %shifted, 7
322431
ret i32 %masked
@@ -335,6 +444,12 @@ define i64 @extu_from_and_lshr_i64(i64 %x) {
335444
; RV32XQCIBM-NEXT: qc.extu a0, a1, 12, 14
336445
; RV32XQCIBM-NEXT: li a1, 0
337446
; RV32XQCIBM-NEXT: ret
447+
;
448+
; RV32XQCIBMZBB-LABEL: extu_from_and_lshr_i64:
449+
; RV32XQCIBMZBB: # %bb.0:
450+
; RV32XQCIBMZBB-NEXT: qc.extu a0, a1, 12, 14
451+
; RV32XQCIBMZBB-NEXT: li a1, 0
452+
; RV32XQCIBMZBB-NEXT: ret
338453
%shifted = lshr i64 %x, 46
339454
%masked = and i64 %shifted, 4095
340455
ret i64 %masked
@@ -351,6 +466,11 @@ define i32 @extu_from_lshr_and_i32(i32 %x) {
351466
; RV32XQCIBM: # %bb.0:
352467
; RV32XQCIBM-NEXT: qc.extu a0, a0, 12, 12
353468
; RV32XQCIBM-NEXT: ret
469+
;
470+
; RV32XQCIBMZBB-LABEL: extu_from_lshr_and_i32:
471+
; RV32XQCIBMZBB: # %bb.0:
472+
; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 12, 12
473+
; RV32XQCIBMZBB-NEXT: ret
354474
%masked = and i32 %x, 16773120
355475
%shifted = lshr i32 %masked, 12
356476
ret i32 %shifted
@@ -369,6 +489,12 @@ define i64 @extu_from_lshr_and_i64(i64 %x) {
369489
; RV32XQCIBM-NEXT: qc.extu a0, a0, 12, 12
370490
; RV32XQCIBM-NEXT: li a1, 0
371491
; RV32XQCIBM-NEXT: ret
492+
;
493+
; RV32XQCIBMZBB-LABEL: extu_from_lshr_and_i64:
494+
; RV32XQCIBMZBB: # %bb.0:
495+
; RV32XQCIBMZBB-NEXT: qc.extu a0, a0, 12, 12
496+
; RV32XQCIBMZBB-NEXT: li a1, 0
497+
; RV32XQCIBMZBB-NEXT: ret
372498
%masked = and i64 %x, 16773120
373499
%shifted = lshr i64 %masked, 12
374500
ret i64 %shifted
@@ -385,6 +511,11 @@ define i32 @ext_from_ashr_shl_i32(i32 %x) {
385511
; RV32XQCIBM: # %bb.0:
386512
; RV32XQCIBM-NEXT: qc.ext a0, a0, 8, 16
387513
; RV32XQCIBM-NEXT: ret
514+
;
515+
; RV32XQCIBMZBB-LABEL: ext_from_ashr_shl_i32:
516+
; RV32XQCIBMZBB: # %bb.0:
517+
; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 8, 16
518+
; RV32XQCIBMZBB-NEXT: ret
388519
%shl = shl i32 %x, 8
389520
%ashr = ashr i32 %shl, 24
390521
ret i32 %ashr
@@ -401,6 +532,11 @@ define i32 @ext_from_ashr_sexti8_i32(i8 %x) {
401532
; RV32XQCIBM: # %bb.0:
402533
; RV32XQCIBM-NEXT: qc.ext a0, a0, 3, 5
403534
; RV32XQCIBM-NEXT: ret
535+
;
536+
; RV32XQCIBMZBB-LABEL: ext_from_ashr_sexti8_i32:
537+
; RV32XQCIBMZBB: # %bb.0:
538+
; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 3, 5
539+
; RV32XQCIBMZBB-NEXT: ret
404540
%sext = sext i8 %x to i32
405541
%ashr = ashr i32 %sext, 5
406542
ret i32 %ashr
@@ -417,6 +553,11 @@ define i32 @ext_from_ashr_sexti16_i32(i16 %x) {
417553
; RV32XQCIBM: # %bb.0:
418554
; RV32XQCIBM-NEXT: qc.ext a0, a0, 1, 15
419555
; RV32XQCIBM-NEXT: ret
556+
;
557+
; RV32XQCIBMZBB-LABEL: ext_from_ashr_sexti16_i32:
558+
; RV32XQCIBMZBB: # %bb.0:
559+
; RV32XQCIBMZBB-NEXT: qc.ext a0, a0, 1, 15
560+
; RV32XQCIBMZBB-NEXT: ret
420561
%sext = sext i16 %x to i32
421562
%ashr = ashr i32 %sext, 24
422563
ret i32 %ashr

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