AMDGPU/GlobalISel: Fix smrd loads of v4i64

arsenm · arsenm · commit 26ebc51a34ea · 2020-03-24T13:44:41.000-04:00
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -578,15 +578,15 @@ def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,
   let AllocationPriority = 16;
 }
 
-def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256Regs)> {
+def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64], 32, (add SGPR_256Regs)> {
   let AllocationPriority = 17;
 }
 
 def TTMP_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add TTMP_256Regs)> {
   let isAllocatable = 0;
 }
 
-def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32,
+def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64], 32,
                              (add SGPR_256, TTMP_256)> {
   // Requires 4 s_mov_b64 to copy
   let CopyCost = 4;
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -808,7 +808,9 @@ foreach vt = SReg_128.RegTypes in {
 defm : SMRD_Pattern <"S_LOAD_DWORDX4", vt>;
 }
 
-defm : SMRD_Pattern <"S_LOAD_DWORDX8",  v8i32>;
+foreach vt = SReg_256.RegTypes in {
+defm : SMRD_Pattern <"S_LOAD_DWORDX8", vt>;
+}
 defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
 
 defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORD",     i32>;

Original file line number	Diff line number	Diff line change
`@@ -578,15 +578,15 @@ def SReg_160 : RegisterClass<"AMDGPU", [v5i32, v5f32], 32,`
`578`	`578`	`let AllocationPriority = 16;`
`579`	`579`	`}`
`580`	`580`
`581`		`-def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256Regs)> {`
	`581`	`+def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64], 32, (add SGPR_256Regs)> {`
`582`	`582`	`let AllocationPriority = 17;`
`583`	`583`	`}`
`584`	`584`
`585`	`585`	`def TTMP_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add TTMP_256Regs)> {`
`586`	`586`	`let isAllocatable = 0;`
`587`	`587`	`}`
`588`	`588`
`589`		`-def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32,`
	`589`	`+def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32, v4i64], 32,`
`590`	`590`	`(add SGPR_256, TTMP_256)> {`
`591`	`591`	`// Requires 4 s_mov_b64 to copy`
`592`	`592`	`let CopyCost = 4;`
Original file line number	Diff line number	Diff line change
`@@ -808,7 +808,9 @@ foreach vt = SReg_128.RegTypes in {`
`808`	`808`	`defm : SMRD_Pattern <"S_LOAD_DWORDX4", vt>;`
`809`	`809`	`}`
`810`	`810`
`811`		`-defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;`
	`811`	`+foreach vt = SReg_256.RegTypes in {`
	`812`	`+defm : SMRD_Pattern <"S_LOAD_DWORDX8", vt>;`
	`813`	`+}`
`812`	`814`	`defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;`
`813`	`815`
`814`	`816`	`defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORD", i32>;`