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PeddleSpamLeon Clarkarsenm
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[AMDGPU] Remove unnecessary add instructions in ctlz.i8 (#77615)
Add custom lowering for ctlz.i8 to avoid multiple add/sub operations. --------- Co-authored-by: Leon Clark <[email protected]> Co-authored-by: Matt Arsenault <[email protected]>
1 parent 9dd0eb9 commit 2759cfa

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+83
-59
lines changed

4 files changed

+83
-59
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -446,6 +446,9 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
446446
{ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF},
447447
MVT::i64, Custom);
448448

449+
for (auto VT : {MVT::i8, MVT::i16})
450+
setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, VT, Custom);
451+
449452
static const MVT::SimpleValueType VectorIntTypes[] = {
450453
MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32, MVT::v6i32, MVT::v7i32,
451454
MVT::v9i32, MVT::v10i32, MVT::v11i32, MVT::v12i32};
@@ -1398,6 +1401,11 @@ void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
13981401
if (SDValue Lowered = lowerFEXP(SDValue(N, 0), DAG))
13991402
Results.push_back(Lowered);
14001403
return;
1404+
case ISD::CTLZ:
1405+
case ISD::CTLZ_ZERO_UNDEF:
1406+
if (auto Lowered = lowerCTLZResults(SDValue(N, 0u), DAG))
1407+
Results.push_back(Lowered);
1408+
return;
14011409
default:
14021410
return;
14031411
}
@@ -3063,6 +3071,26 @@ static bool isCttzOpc(unsigned Opc) {
30633071
return Opc == ISD::CTTZ || Opc == ISD::CTTZ_ZERO_UNDEF;
30643072
}
30653073

3074+
SDValue AMDGPUTargetLowering::lowerCTLZResults(SDValue Op,
3075+
SelectionDAG &DAG) const {
3076+
auto SL = SDLoc(Op);
3077+
auto Arg = Op.getOperand(0u);
3078+
auto ResultVT = Op.getValueType();
3079+
3080+
if (ResultVT != MVT::i8 && ResultVT != MVT::i16)
3081+
return {};
3082+
3083+
assert(isCtlzOpc(Op.getOpcode()));
3084+
assert(ResultVT == Arg.getValueType());
3085+
3086+
auto const LeadingZeroes = 32u - ResultVT.getFixedSizeInBits();
3087+
auto NewOp = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Arg);
3088+
auto ShiftVal = DAG.getConstant(LeadingZeroes, SL, MVT::i32);
3089+
NewOp = DAG.getNode(ISD::SHL, SL, MVT::i32, NewOp, ShiftVal);
3090+
NewOp = DAG.getNode(Op.getOpcode(), SL, MVT::i32, NewOp);
3091+
return DAG.getNode(ISD::TRUNCATE, SL, ResultVT, NewOp);
3092+
}
3093+
30663094
SDValue AMDGPUTargetLowering::LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const {
30673095
SDLoc SL(Op);
30683096
SDValue Src = Op.getOperand(0);

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,8 @@ class AMDGPUTargetLowering : public TargetLowering {
8484
SDNodeFlags Flags) const;
8585
SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
8686

87+
SDValue lowerCTLZResults(SDValue Op, SelectionDAG &DAG) const;
88+
8789
SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
8890

8991
SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;

‎llvm/test/CodeGen/AMDGPU/ctlz.ll

Lines changed: 14 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -492,9 +492,9 @@ define amdgpu_kernel void @v_ctlz_i8(ptr addrspace(1) noalias %out, ptr addrspac
492492
; SI-NEXT: s_mov_b32 s4, s0
493493
; SI-NEXT: s_mov_b32 s5, s1
494494
; SI-NEXT: s_waitcnt vmcnt(0)
495+
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
495496
; SI-NEXT: v_ffbh_u32_e32 v0, v0
496497
; SI-NEXT: v_min_u32_e32 v0, 32, v0
497-
; SI-NEXT: v_subrev_i32_e32 v0, vcc, 24, v0
498498
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
499499
; SI-NEXT: s_endpgm
500500
;
@@ -512,18 +512,17 @@ define amdgpu_kernel void @v_ctlz_i8(ptr addrspace(1) noalias %out, ptr addrspac
512512
; VI-NEXT: s_mov_b32 s4, s0
513513
; VI-NEXT: s_mov_b32 s5, s1
514514
; VI-NEXT: s_waitcnt vmcnt(0)
515+
; VI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
515516
; VI-NEXT: v_ffbh_u32_e32 v0, v0
516517
; VI-NEXT: v_min_u32_e32 v0, 32, v0
517-
; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0
518-
; VI-NEXT: v_add_u16_e32 v0, -8, v0
519518
; VI-NEXT: buffer_store_byte v0, off, s[4:7], 0
520519
; VI-NEXT: s_endpgm
521520
;
522521
; EG-LABEL: v_ctlz_i8:
523522
; EG: ; %bb.0:
524523
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
525524
; EG-NEXT: TEX 0 @6
526-
; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[]
525+
; EG-NEXT: ALU 16, @9, KC0[CB0:0-32], KC1[]
527526
; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
528527
; EG-NEXT: CF_END
529528
; EG-NEXT: PAD
@@ -532,14 +531,15 @@ define amdgpu_kernel void @v_ctlz_i8(ptr addrspace(1) noalias %out, ptr addrspac
532531
; EG-NEXT: ALU clause starting at 8:
533532
; EG-NEXT: MOV * T0.X, KC0[2].Z,
534533
; EG-NEXT: ALU clause starting at 9:
535-
; EG-NEXT: FFBH_UINT * T0.W, T0.X,
536-
; EG-NEXT: CNDE_INT T0.W, T0.X, literal.x, PV.W,
537-
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
538-
; EG-NEXT: 32(4.484155e-44), 3(4.203895e-45)
539-
; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,
540-
; EG-NEXT: -24(nan), 0(0.000000e+00)
534+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
535+
; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
536+
; EG-NEXT: FFBH_UINT T1.W, PV.W,
537+
; EG-NEXT: AND_INT * T2.W, KC0[2].Y, literal.x,
538+
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
539+
; EG-NEXT: CNDE_INT * T0.W, T0.W, literal.x, PV.W,
540+
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
541541
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
542-
; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
542+
; EG-NEXT: LSHL * T1.W, T2.W, literal.y,
543543
; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)
544544
; EG-NEXT: LSHL T0.X, PV.W, PS,
545545
; EG-NEXT: LSHL * T0.W, literal.x, PS,
@@ -556,10 +556,9 @@ define amdgpu_kernel void @v_ctlz_i8(ptr addrspace(1) noalias %out, ptr addrspac
556556
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
557557
; GFX10-NEXT: global_load_ubyte v1, v0, s[2:3]
558558
; GFX10-NEXT: s_waitcnt vmcnt(0)
559+
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 24, v1
559560
; GFX10-NEXT: v_ffbh_u32_e32 v1, v1
560561
; GFX10-NEXT: v_min_u32_e32 v1, 32, v1
561-
; GFX10-NEXT: v_add_nc_u32_e32 v1, -16, v1
562-
; GFX10-NEXT: v_add_nc_u16 v1, v1, -8
563562
; GFX10-NEXT: global_store_byte v0, v1, s[0:1]
564563
; GFX10-NEXT: s_endpgm
565564
;
@@ -583,12 +582,10 @@ define amdgpu_kernel void @v_ctlz_i8(ptr addrspace(1) noalias %out, ptr addrspac
583582
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
584583
; GFX11-NEXT: global_load_u8 v1, v0, s[2:3]
585584
; GFX11-NEXT: s_waitcnt vmcnt(0)
586-
; GFX11-NEXT: v_clz_i32_u32_e32 v1, v1
585+
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1
587586
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
587+
; GFX11-NEXT: v_clz_i32_u32_e32 v1, v1
588588
; GFX11-NEXT: v_min_u32_e32 v1, 32, v1
589-
; GFX11-NEXT: v_add_nc_u32_e32 v1, -16, v1
590-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
591-
; GFX11-NEXT: v_add_nc_u16 v1, v1, -8
592589
; GFX11-NEXT: global_store_b8 v0, v1, s[0:1]
593590
; GFX11-NEXT: s_nop 0
594591
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)

‎llvm/test/CodeGen/AMDGPU/ctlz_zero_undef.ll

Lines changed: 39 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -314,9 +314,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
314314
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
315315
; SI-NEXT: s_mov_b32 s3, 0xf000
316316
; SI-NEXT: s_waitcnt lgkmcnt(0)
317-
; SI-NEXT: s_and_b32 s2, s2, 0xff
318-
; SI-NEXT: s_flbit_i32_b32 s2, s2
319-
; SI-NEXT: s_sub_i32 s4, s2, 24
317+
; SI-NEXT: s_lshl_b32 s2, s2, 24
318+
; SI-NEXT: s_flbit_i32_b32 s4, s2
320319
; SI-NEXT: s_mov_b32 s2, -1
321320
; SI-NEXT: v_mov_b32_e32 v0, s4
322321
; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
@@ -327,12 +326,11 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
327326
; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
328327
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
329328
; VI-NEXT: s_waitcnt lgkmcnt(0)
330-
; VI-NEXT: s_and_b32 s2, s2, 0xff
329+
; VI-NEXT: s_lshl_b32 s2, s2, 24
331330
; VI-NEXT: s_flbit_i32_b32 s2, s2
332-
; VI-NEXT: s_add_i32 s2, s2, -16
333331
; VI-NEXT: v_mov_b32_e32 v0, s0
334-
; VI-NEXT: v_add_u16_e64 v2, s2, -8
335332
; VI-NEXT: v_mov_b32_e32 v1, s1
333+
; VI-NEXT: v_mov_b32_e32 v2, s2
336334
; VI-NEXT: flat_store_byte v[0:1], v2
337335
; VI-NEXT: s_endpgm
338336
;
@@ -349,13 +347,13 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
349347
; EG-NEXT: ALU clause starting at 8:
350348
; EG-NEXT: MOV * T0.X, 0.0,
351349
; EG-NEXT: ALU clause starting at 9:
352-
; EG-NEXT: FFBH_UINT T0.W, T0.X,
350+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
351+
; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
352+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
353353
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
354354
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
355-
; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,
356-
; EG-NEXT: -24(nan), 0(0.000000e+00)
357355
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
358-
; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
356+
; EG-NEXT: LSHL * T1.W, PS, literal.y,
359357
; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)
360358
; EG-NEXT: LSHL T0.X, PV.W, PS,
361359
; EG-NEXT: LSHL * T0.W, literal.x, PS,
@@ -391,9 +389,8 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
391389
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
392390
; SI-NEXT: s_mov_b32 s3, 0xf000
393391
; SI-NEXT: s_waitcnt lgkmcnt(0)
394-
; SI-NEXT: s_and_b32 s2, s2, 0xffff
395-
; SI-NEXT: s_flbit_i32_b32 s2, s2
396-
; SI-NEXT: s_add_i32 s4, s2, -16
392+
; SI-NEXT: s_lshl_b32 s2, s2, 16
393+
; SI-NEXT: s_flbit_i32_b32 s4, s2
397394
; SI-NEXT: s_mov_b32 s2, -1
398395
; SI-NEXT: v_mov_b32_e32 v0, s4
399396
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
@@ -426,13 +423,13 @@ define amdgpu_kernel void @s_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
426423
; EG-NEXT: ALU clause starting at 8:
427424
; EG-NEXT: MOV * T0.X, 0.0,
428425
; EG-NEXT: ALU clause starting at 9:
429-
; EG-NEXT: FFBH_UINT T0.W, T0.X,
426+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
427+
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
428+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
430429
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
431430
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
432-
; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,
433-
; EG-NEXT: -16(nan), 0(0.000000e+00)
434431
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
435-
; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
432+
; EG-NEXT: LSHL * T1.W, PS, literal.y,
436433
; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
437434
; EG-NEXT: LSHL T0.X, PV.W, PS,
438435
; EG-NEXT: LSHL * T0.W, literal.x, PS,
@@ -590,8 +587,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
590587
; SI-NEXT: s_mov_b32 s4, s0
591588
; SI-NEXT: s_mov_b32 s5, s1
592589
; SI-NEXT: s_waitcnt vmcnt(0)
593-
; SI-NEXT: v_ffbh_u32_e32 v1, v0
594-
; SI-NEXT: v_subrev_i32_e32 v1, vcc, 24, v1
590+
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v0
591+
; SI-NEXT: v_ffbh_u32_e32 v1, v1
595592
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
596593
; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc
597594
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
@@ -605,9 +602,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
605602
; VI-NEXT: v_mov_b32_e32 v1, s3
606603
; VI-NEXT: flat_load_ubyte v0, v[0:1]
607604
; VI-NEXT: s_waitcnt vmcnt(0)
608-
; VI-NEXT: v_ffbh_u32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
609-
; VI-NEXT: v_add_u32_e32 v1, vcc, -16, v1
610-
; VI-NEXT: v_add_u16_e32 v1, -8, v1
605+
; VI-NEXT: v_lshlrev_b32_e32 v1, 24, v0
606+
; VI-NEXT: v_ffbh_u32_e32 v1, v1
611607
; VI-NEXT: v_cmp_ne_u16_e32 vcc, 0, v0
612608
; VI-NEXT: v_cndmask_b32_e32 v2, 32, v1, vcc
613609
; VI-NEXT: v_mov_b32_e32 v0, s0
@@ -619,7 +615,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
619615
; EG: ; %bb.0:
620616
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
621617
; EG-NEXT: TEX 0 @6
622-
; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[]
618+
; EG-NEXT: ALU 16, @9, KC0[CB0:0-32], KC1[]
623619
; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
624620
; EG-NEXT: CF_END
625621
; EG-NEXT: PAD
@@ -628,10 +624,11 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8_with_select(ptr addrspace(1) noa
628624
; EG-NEXT: ALU clause starting at 8:
629625
; EG-NEXT: MOV * T0.X, KC0[2].Z,
630626
; EG-NEXT: ALU clause starting at 9:
631-
; EG-NEXT: FFBH_UINT * T0.W, T0.X,
632-
; EG-NEXT: ADD_INT T0.W, PV.W, literal.x,
633-
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
634-
; EG-NEXT: -24(nan), 3(4.203895e-45)
627+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
628+
; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
629+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
630+
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
631+
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
635632
; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,
636633
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
637634
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
@@ -686,8 +683,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
686683
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
687684
; SI-NEXT: s_waitcnt vmcnt(0)
688685
; SI-NEXT: v_or_b32_e32 v0, v0, v1
689-
; SI-NEXT: v_ffbh_u32_e32 v1, v0
690-
; SI-NEXT: v_add_i32_e32 v1, vcc, -16, v1
686+
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
687+
; SI-NEXT: v_ffbh_u32_e32 v1, v1
691688
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
692689
; SI-NEXT: v_cndmask_b32_e32 v0, 32, v1, vcc
693690
; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
@@ -722,7 +719,7 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
722719
; EG: ; %bb.0:
723720
; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
724721
; EG-NEXT: TEX 0 @6
725-
; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[]
722+
; EG-NEXT: ALU 16, @9, KC0[CB0:0-32], KC1[]
726723
; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
727724
; EG-NEXT: CF_END
728725
; EG-NEXT: PAD
@@ -731,10 +728,11 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i16_with_select(ptr addrspace(1) no
731728
; EG-NEXT: ALU clause starting at 8:
732729
; EG-NEXT: MOV * T0.X, KC0[2].Z,
733730
; EG-NEXT: ALU clause starting at 9:
734-
; EG-NEXT: FFBH_UINT * T0.W, T0.X,
735-
; EG-NEXT: ADD_INT T0.W, PV.W, literal.x,
736-
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
737-
; EG-NEXT: -16(nan), 3(4.203895e-45)
731+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
732+
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
733+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
734+
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
735+
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
738736
; EG-NEXT: CNDE_INT * T0.W, T0.X, literal.x, PV.W,
739737
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
740738
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
@@ -1103,8 +1101,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
11031101
; SI-NEXT: s_mov_b32 s4, s0
11041102
; SI-NEXT: s_mov_b32 s5, s1
11051103
; SI-NEXT: s_waitcnt vmcnt(0)
1104+
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
11061105
; SI-NEXT: v_ffbh_u32_e32 v0, v0
1107-
; SI-NEXT: v_subrev_i32_e32 v0, vcc, 24, v0
11081106
; SI-NEXT: buffer_store_byte v0, off, s[4:7], 0
11091107
; SI-NEXT: s_endpgm
11101108
;
@@ -1117,9 +1115,8 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
11171115
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
11181116
; VI-NEXT: flat_load_ubyte v0, v[0:1]
11191117
; VI-NEXT: s_waitcnt vmcnt(0)
1120-
; VI-NEXT: v_ffbh_u32_e32 v0, v0
1121-
; VI-NEXT: v_add_u32_e32 v0, vcc, -16, v0
1122-
; VI-NEXT: v_add_u16_e32 v2, -8, v0
1118+
; VI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
1119+
; VI-NEXT: v_ffbh_u32_e32 v2, v0
11231120
; VI-NEXT: v_mov_b32_e32 v0, s0
11241121
; VI-NEXT: v_mov_b32_e32 v1, s1
11251122
; VI-NEXT: flat_store_byte v[0:1], v2
@@ -1138,13 +1135,13 @@ define amdgpu_kernel void @v_ctlz_zero_undef_i8(ptr addrspace(1) noalias %out, p
11381135
; EG-NEXT: ALU clause starting at 8:
11391136
; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, T0.X,
11401137
; EG-NEXT: ALU clause starting at 9:
1141-
; EG-NEXT: FFBH_UINT T0.W, T0.X,
1138+
; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
1139+
; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
1140+
; EG-NEXT: FFBH_UINT T0.W, PV.W,
11421141
; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.x,
11431142
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
1144-
; EG-NEXT: ADD_INT * T0.W, PV.W, literal.x,
1145-
; EG-NEXT: -24(nan), 0(0.000000e+00)
11461143
; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
1147-
; EG-NEXT: LSHL * T1.W, T1.W, literal.y,
1144+
; EG-NEXT: LSHL * T1.W, PS, literal.y,
11481145
; EG-NEXT: 255(3.573311e-43), 3(4.203895e-45)
11491146
; EG-NEXT: LSHL T0.X, PV.W, PS,
11501147
; EG-NEXT: LSHL * T0.W, literal.x, PS,

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