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| 1 | +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ |
| 2 | +// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \ |
| 3 | +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \ |
| 4 | +// RUN: --check-prefixes=CHECK,DXIL_CHECK,DXIL_NATIVE_HALF,NATIVE_HALF |
| 5 | +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ |
| 6 | +// RUN: dxil-pc-shadermodel6.3-library %s -emit-llvm -disable-llvm-passes \ |
| 7 | +// RUN: -o - | FileCheck %s --check-prefixes=CHECK,DXIL_CHECK,NO_HALF,DXIL_NO_HALF |
| 8 | +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ |
| 9 | +// RUN: spirv-unknown-vulkan-compute %s -fnative-half-type \ |
| 10 | +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \ |
| 11 | +// RUN: --check-prefixes=CHECK,SPIR_CHECK,NATIVE_HALF,SPIR_NATIVE_HALF |
| 12 | +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ |
| 13 | +// RUN: spirv-unknown-vulkan-compute %s -emit-llvm -disable-llvm-passes \ |
| 14 | +// RUN: -o - | FileCheck %s --check-prefixes=CHECK,SPIR_CHECK,NO_HALF,SPIR_NO_HALF |
| 15 | + |
| 16 | +// DXIL_NATIVE_HALF: define noundef i32 @ |
| 17 | +// SPIR_NATIVE_HALF: define spir_func noundef i32 @ |
| 18 | +// DXIL_NATIVE_HALF: %hlsl.sign = call i32 @llvm.dx.sign.f16( |
| 19 | +// SPIR_NATIVE_HALF: %hlsl.sign = call i32 @llvm.spv.sign.f16( |
| 20 | +// NATIVE_HALF: ret i32 %hlsl.sign |
| 21 | +// DXIL_NO_HALF: define noundef i32 @ |
| 22 | +// SPIR_NO_HALF: define spir_func noundef i32 @ |
| 23 | +// DXIL_NO_HALF: %hlsl.sign = call i32 @llvm.dx.sign.f32( |
| 24 | +// SPIR_NO_HALF: %hlsl.sign = call i32 @llvm.spv.sign.f32( |
| 25 | +// NO_HALF: ret i32 %hlsl.sign |
| 26 | +int test_sign_half(half p0) { return sign(p0); } |
| 27 | + |
| 28 | +// DXIL_NATIVE_HALF: define noundef <2 x i32> @ |
| 29 | +// SPIR_NATIVE_HALF: define spir_func noundef <2 x i32> @ |
| 30 | +// DXIL_NATIVE_HALF: %hlsl.sign = call <2 x i32> @llvm.dx.sign.v2f16( |
| 31 | +// SPIR_NATIVE_HALF: %hlsl.sign = call <2 x i32> @llvm.spv.sign.v2f16( |
| 32 | +// NATIVE_HALF: ret <2 x i32> %hlsl.sign |
| 33 | +// DXIL_NO_HALF: define noundef <2 x i32> @ |
| 34 | +// SPIR_NO_HALF: define spir_func noundef <2 x i32> @ |
| 35 | +// DXIL_NO_HALF: %hlsl.sign = call <2 x i32> @llvm.dx.sign.v2f32( |
| 36 | +// SPIR_NO_HALF: %hlsl.sign = call <2 x i32> @llvm.spv.sign.v2f32( |
| 37 | +// NO_HALF: ret <2 x i32> %hlsl.sign |
| 38 | +int2 test_sign_half2(half2 p0) { return sign(p0); } |
| 39 | + |
| 40 | +// DXIL_NATIVE_HALF: define noundef <3 x i32> @ |
| 41 | +// SPIR_NATIVE_HALF: define spir_func noundef <3 x i32> @ |
| 42 | +// DXIL_NATIVE_HALF: %hlsl.sign = call <3 x i32> @llvm.dx.sign.v3f16( |
| 43 | +// SPIR_NATIVE_HALF: %hlsl.sign = call <3 x i32> @llvm.spv.sign.v3f16( |
| 44 | +// NATIVE_HALF: ret <3 x i32> %hlsl.sign |
| 45 | +// DXIL_NO_HALF: define noundef <3 x i32> @ |
| 46 | +// SPIR_NO_HALF: define spir_func noundef <3 x i32> @ |
| 47 | +// DXIL_NO_HALF: %hlsl.sign = call <3 x i32> @llvm.dx.sign.v3f32( |
| 48 | +// SPIR_NO_HALF: %hlsl.sign = call <3 x i32> @llvm.spv.sign.v3f32( |
| 49 | +// NO_HALF: ret <3 x i32> %hlsl.sign |
| 50 | +int3 test_sign_half3(half3 p0) { return sign(p0); } |
| 51 | + |
| 52 | +// DXIL_NATIVE_HALF: define noundef <4 x i32> @ |
| 53 | +// SPIR_NATIVE_HALF: define spir_func noundef <4 x i32> @ |
| 54 | +// DXIL_NATIVE_HALF: %hlsl.sign = call <4 x i32> @llvm.dx.sign.v4f16( |
| 55 | +// SPIR_NATIVE_HALF: %hlsl.sign = call <4 x i32> @llvm.spv.sign.v4f16( |
| 56 | +// NATIVE_HALF: ret <4 x i32> %hlsl.sign |
| 57 | +// DXIL_NO_HALF: define noundef <4 x i32> @ |
| 58 | +// SPIR_NO_HALF: define spir_func noundef <4 x i32> @ |
| 59 | +// DXIL_NO_HALF: %hlsl.sign = call <4 x i32> @llvm.dx.sign.v4f32( |
| 60 | +// SPIR_NO_HALF: %hlsl.sign = call <4 x i32> @llvm.spv.sign.v4f32( |
| 61 | +// NO_HALF: ret <4 x i32> %hlsl.sign |
| 62 | +int4 test_sign_half4(half4 p0) { return sign(p0); } |
| 63 | + |
| 64 | + |
| 65 | +// DXIL_CHECK: define noundef i32 @ |
| 66 | +// SPIR_CHECK: define spir_func noundef i32 @ |
| 67 | +// DXIL_CHECK: %hlsl.sign = call i32 @llvm.dx.sign.f32( |
| 68 | +// SPIR_CHECK: %hlsl.sign = call i32 @llvm.spv.sign.f32( |
| 69 | +// CHECK: ret i32 %hlsl.sign |
| 70 | +int test_sign_float(float p0) { return sign(p0); } |
| 71 | + |
| 72 | +// DXIL_CHECK: define noundef <2 x i32> @ |
| 73 | +// SPIR_CHECK: define spir_func noundef <2 x i32> @ |
| 74 | +// DXIL_CHECK: %hlsl.sign = call <2 x i32> @llvm.dx.sign.v2f32( |
| 75 | +// SPIR_CHECK: %hlsl.sign = call <2 x i32> @llvm.spv.sign.v2f32( |
| 76 | +// CHECK: ret <2 x i32> %hlsl.sign |
| 77 | +int2 test_sign_float2(float2 p0) { return sign(p0); } |
| 78 | + |
| 79 | +// DXIL_CHECK: define noundef <3 x i32> @ |
| 80 | +// SPIR_CHECK: define spir_func noundef <3 x i32> @ |
| 81 | +// DXIL_CHECK: %hlsl.sign = call <3 x i32> @llvm.dx.sign.v3f32( |
| 82 | +// SPIR_CHECK: %hlsl.sign = call <3 x i32> @llvm.spv.sign.v3f32( |
| 83 | +// CHECK: ret <3 x i32> %hlsl.sign |
| 84 | +int3 test_sign_float3(float3 p0) { return sign(p0); } |
| 85 | + |
| 86 | +// DXIL_CHECK: define noundef <4 x i32> @ |
| 87 | +// SPIR_CHECK: define spir_func noundef <4 x i32> @ |
| 88 | +// DXIL_CHECK: %hlsl.sign = call <4 x i32> @llvm.dx.sign.v4f32( |
| 89 | +// SPIR_CHECK: %hlsl.sign = call <4 x i32> @llvm.spv.sign.v4f32( |
| 90 | +// CHECK: ret <4 x i32> %hlsl.sign |
| 91 | +int4 test_sign_float4(float4 p0) { return sign(p0); } |
| 92 | + |
| 93 | + |
| 94 | +// DXIL_CHECK: define noundef i32 @ |
| 95 | +// SPIR_CHECK: define spir_func noundef i32 @ |
| 96 | +// DXIL_CHECK: %hlsl.sign = call i32 @llvm.dx.sign.f64( |
| 97 | +// SPIR_CHECK: %hlsl.sign = call i32 @llvm.spv.sign.f64( |
| 98 | +// CHECK: ret i32 %hlsl.sign |
| 99 | +int test_sign_double(double p0) { return sign(p0); } |
| 100 | + |
| 101 | +// DXIL_CHECK: define noundef <2 x i32> @ |
| 102 | +// SPIR_CHECK: define spir_func noundef <2 x i32> @ |
| 103 | +// DXIL_CHECK: %hlsl.sign = call <2 x i32> @llvm.dx.sign.v2f64( |
| 104 | +// SPIR_CHECK: %hlsl.sign = call <2 x i32> @llvm.spv.sign.v2f64( |
| 105 | +// CHECK: ret <2 x i32> %hlsl.sign |
| 106 | +int2 test_sign_double2(double2 p0) { return sign(p0); } |
| 107 | + |
| 108 | +// DXIL_CHECK: define noundef <3 x i32> @ |
| 109 | +// SPIR_CHECK: define spir_func noundef <3 x i32> @ |
| 110 | +// DXIL_CHECK: %hlsl.sign = call <3 x i32> @llvm.dx.sign.v3f64( |
| 111 | +// SPIR_CHECK: %hlsl.sign = call <3 x i32> @llvm.spv.sign.v3f64( |
| 112 | +// CHECK: ret <3 x i32> %hlsl.sign |
| 113 | +int3 test_sign_double3(double3 p0) { return sign(p0); } |
| 114 | + |
| 115 | +// DXIL_CHECK: define noundef <4 x i32> @ |
| 116 | +// SPIR_CHECK: define spir_func noundef <4 x i32> @ |
| 117 | +// DXIL_CHECK: %hlsl.sign = call <4 x i32> @llvm.dx.sign.v4f64( |
| 118 | +// SPIR_CHECK: %hlsl.sign = call <4 x i32> @llvm.spv.sign.v4f64( |
| 119 | +// CHECK: ret <4 x i32> %hlsl.sign |
| 120 | +int4 test_sign_double4(double4 p0) { return sign(p0); } |
| 121 | + |
| 122 | + |
| 123 | +#ifdef __HLSL_ENABLE_16_BIT |
| 124 | +// DXIL_NATIVE_HALF: define noundef i32 @ |
| 125 | +// SPIR_NATIVE_HALF: define spir_func noundef i32 @ |
| 126 | +// DXIL_NATIVE_HALF: %hlsl.sign = call i32 @llvm.dx.sign.i16( |
| 127 | +// SPIR_NATIVE_HALF: %hlsl.sign = call i32 @llvm.spv.sign.i16( |
| 128 | +// NATIVE_HALF: ret i32 %hlsl.sign |
| 129 | +int test_sign_int16_t(int16_t p0) { return sign(p0); } |
| 130 | + |
| 131 | +// DXIL_NATIVE_HALF: define noundef <2 x i32> @ |
| 132 | +// SPIR_NATIVE_HALF: define spir_func noundef <2 x i32> @ |
| 133 | +// DXIL_NATIVE_HALF: %hlsl.sign = call <2 x i32> @llvm.dx.sign.v2i16( |
| 134 | +// SPIR_NATIVE_HALF: %hlsl.sign = call <2 x i32> @llvm.spv.sign.v2i16( |
| 135 | +// NATIVE_HALF: ret <2 x i32> %hlsl.sign |
| 136 | +int2 test_sign_int16_t2(int16_t2 p0) { return sign(p0); } |
| 137 | + |
| 138 | +// DXIL_NATIVE_HALF: define noundef <3 x i32> @ |
| 139 | +// SPIR_NATIVE_HALF: define spir_func noundef <3 x i32> @ |
| 140 | +// DXIL_NATIVE_HALF: %hlsl.sign = call <3 x i32> @llvm.dx.sign.v3i16( |
| 141 | +// SPIR_NATIVE_HALF: %hlsl.sign = call <3 x i32> @llvm.spv.sign.v3i16( |
| 142 | +// NATIVE_HALF: ret <3 x i32> %hlsl.sign |
| 143 | +int3 test_sign_int16_t3(int16_t3 p0) { return sign(p0); } |
| 144 | + |
| 145 | +// DXIL_NATIVE_HALF: define noundef <4 x i32> @ |
| 146 | +// SPIR_NATIVE_HALF: define spir_func noundef <4 x i32> @ |
| 147 | +// DXIL_NATIVE_HALF: %hlsl.sign = call <4 x i32> @llvm.dx.sign.v4i16( |
| 148 | +// SPIR_NATIVE_HALF: %hlsl.sign = call <4 x i32> @llvm.spv.sign.v4i16( |
| 149 | +// NATIVE_HALF: ret <4 x i32> %hlsl.sign |
| 150 | +int4 test_sign_int16_t4(int16_t4 p0) { return sign(p0); } |
| 151 | +#endif // __HLSL_ENABLE_16_BIT |
| 152 | + |
| 153 | + |
| 154 | +// DXIL_CHECK: define noundef i32 @ |
| 155 | +// SPIR_CHECK: define spir_func noundef i32 @ |
| 156 | +// DXIL_CHECK: %hlsl.sign = call i32 @llvm.dx.sign.i32( |
| 157 | +// SPIR_CHECK: %hlsl.sign = call i32 @llvm.spv.sign.i32( |
| 158 | +// CHECK: ret i32 %hlsl.sign |
| 159 | +int test_sign_int(int p0) { return sign(p0); } |
| 160 | + |
| 161 | +// DXIL_CHECK: define noundef <2 x i32> @ |
| 162 | +// SPIR_CHECK: define spir_func noundef <2 x i32> @ |
| 163 | +// DXIL_CHECK: %hlsl.sign = call <2 x i32> @llvm.dx.sign.v2i32( |
| 164 | +// SPIR_CHECK: %hlsl.sign = call <2 x i32> @llvm.spv.sign.v2i32( |
| 165 | +// CHECK: ret <2 x i32> %hlsl.sign |
| 166 | +int2 test_sign_int2(int2 p0) { return sign(p0); } |
| 167 | + |
| 168 | +// DXIL_CHECK: define noundef <3 x i32> @ |
| 169 | +// SPIR_CHECK: define spir_func noundef <3 x i32> @ |
| 170 | +// DXIL_CHECK: %hlsl.sign = call <3 x i32> @llvm.dx.sign.v3i32( |
| 171 | +// SPIR_CHECK: %hlsl.sign = call <3 x i32> @llvm.spv.sign.v3i32( |
| 172 | +// CHECK: ret <3 x i32> %hlsl.sign |
| 173 | +int3 test_sign_int3(int3 p0) { return sign(p0); } |
| 174 | + |
| 175 | +// DXIL_CHECK: define noundef <4 x i32> @ |
| 176 | +// SPIR_CHECK: define spir_func noundef <4 x i32> @ |
| 177 | +// DXIL_CHECK: %hlsl.sign = call <4 x i32> @llvm.dx.sign.v4i32( |
| 178 | +// SPIR_CHECK: %hlsl.sign = call <4 x i32> @llvm.spv.sign.v4i32( |
| 179 | +// CHECK: ret <4 x i32> %hlsl.sign |
| 180 | +int4 test_sign_int4(int4 p0) { return sign(p0); } |
| 181 | + |
| 182 | + |
| 183 | +// DXIL_CHECK: define noundef i32 @ |
| 184 | +// SPIR_CHECK: define spir_func noundef i32 @ |
| 185 | +// DXIL_CHECK: %hlsl.sign = call i32 @llvm.dx.sign.i64( |
| 186 | +// SPIR_CHECK: %hlsl.sign = call i32 @llvm.spv.sign.i64( |
| 187 | +// CHECK: ret i32 %hlsl.sign |
| 188 | +int test_sign_int64_t(int64_t p0) { return sign(p0); } |
| 189 | + |
| 190 | +// DXIL_CHECK: define noundef <2 x i32> @ |
| 191 | +// SPIR_CHECK: define spir_func noundef <2 x i32> @ |
| 192 | +// DXIL_CHECK: %hlsl.sign = call <2 x i32> @llvm.dx.sign.v2i64( |
| 193 | +// SPIR_CHECK: %hlsl.sign = call <2 x i32> @llvm.spv.sign.v2i64( |
| 194 | +// CHECK: ret <2 x i32> %hlsl.sign |
| 195 | +int2 test_sign_int64_t2(int64_t2 p0) { return sign(p0); } |
| 196 | + |
| 197 | +// DXIL_CHECK: define noundef <3 x i32> @ |
| 198 | +// SPIR_CHECK: define spir_func noundef <3 x i32> @ |
| 199 | +// DXIL_CHECK: %hlsl.sign = call <3 x i32> @llvm.dx.sign.v3i64( |
| 200 | +// SPIR_CHECK: %hlsl.sign = call <3 x i32> @llvm.spv.sign.v3i64( |
| 201 | +// CHECK: ret <3 x i32> %hlsl.sign |
| 202 | +int3 test_sign_int64_t3(int64_t3 p0) { return sign(p0); } |
| 203 | + |
| 204 | +// DXIL_CHECK: define noundef <4 x i32> @ |
| 205 | +// SPIR_CHECK: define spir_func noundef <4 x i32> @ |
| 206 | +// DXIL_CHECK: %hlsl.sign = call <4 x i32> @llvm.dx.sign.v4i64( |
| 207 | +// SPIR_CHECK: %hlsl.sign = call <4 x i32> @llvm.spv.sign.v4i64( |
| 208 | +// CHECK: ret <4 x i32> %hlsl.sign |
| 209 | +int4 test_sign_int64_t4(int64_t4 p0) { return sign(p0); } |
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