@@ -2926,8 +2926,8 @@ define i8 @select_replacement_loop3(i32 noundef %x) {
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define i16 @select_replacement_loop4 (i16 noundef %p_12 ) {
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; CHECK-LABEL: @select_replacement_loop4(
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; CHECK-NEXT: [[AND1:%.*]] = and i16 [[P_12:%.*]], 1
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- ; CHECK-NEXT: [[CMP2 :%.*]] = icmp ult i16 [[P_12]], 2
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- ; CHECK-NEXT: [[AND3:%.*]] = select i1 [[CMP2 ]], i16 [[AND1]], i16 0
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+ ; CHECK-NEXT: [[CMP21 :%.*]] = icmp ult i16 [[P_12]], 2
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+ ; CHECK-NEXT: [[AND3:%.*]] = select i1 [[CMP21 ]], i16 [[AND1]], i16 0
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; CHECK-NEXT: ret i16 [[AND3]]
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;
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%cmp1 = icmp ult i16 %p_12 , 2
@@ -3113,8 +3113,8 @@ define <4 x i32> @mul_select_eq_zero_vector(<4 x i32> %x, <4 x i32> %y) {
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; select (<k x elt> x == {0, poison, ...}), <k x elt> 0, <k x elt> x * y --> freeze(y) * x
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define <2 x i32 > @mul_select_eq_poison_vector (<2 x i32 > %x , <2 x i32 > %y ) {
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; CHECK-LABEL: @mul_select_eq_poison_vector(
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- ; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i32> [[Y_FR :%.*]], <i32 0, i32 poison>
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- ; CHECK-NEXT: [[M:%.*]] = mul <2 x i32> [[Y_FR ]], [[X :%.*]]
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+ ; CHECK-NEXT: [[C:%.*]] = icmp eq <2 x i32> [[X :%.*]], <i32 0, i32 poison>
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+ ; CHECK-NEXT: [[M:%.*]] = mul <2 x i32> [[X ]], [[Y :%.*]]
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; CHECK-NEXT: [[R:%.*]] = select <2 x i1> [[C]], <2 x i32> <i32 0, i32 42>, <2 x i32> [[M]]
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
@@ -3830,6 +3830,26 @@ entry:
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ret i32 %cond
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}
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+ ; FIXME: This is a miscompile.
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+ define <2 x i32 > @src_and_eq_C_xor_OrAndNotC_vec_poison (<2 x i32 > %0 , <2 x i32 > %1 , <2 x i32 > %2 ) {
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+ ; CHECK-LABEL: @src_and_eq_C_xor_OrAndNotC_vec_poison(
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+ ; CHECK-NEXT: entry:
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+ ; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[TMP1:%.*]], [[TMP0:%.*]]
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+ ; CHECK-NEXT: [[NOT:%.*]] = xor <2 x i32> [[TMP2:%.*]], <i32 -1, i32 poison>
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+ ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[OR]], [[NOT]]
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+ ; CHECK-NEXT: ret <2 x i32> [[AND1]]
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+ ;
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+ entry:
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+ %and = and <2 x i32 > %1 , %0
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+ %cmp = icmp eq <2 x i32 > %and , %2
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+ %xor = xor <2 x i32 > %1 , %0
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+ %or = or <2 x i32 > %1 , %0
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+ %not = xor <2 x i32 > %2 , <i32 -1 , i32 poison>
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+ %and1 = and <2 x i32 > %or , %not
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+ %cond = select <2 x i1 > %cmp , <2 x i32 > %xor , <2 x i32 > %and1
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+ ret <2 x i32 > %cond
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+ }
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+
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define i32 @src_and_eq_C_xor_orxorC (i32 %x , i32 %y , i32 %c ) {
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; CHECK-LABEL: @src_and_eq_C_xor_orxorC(
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; CHECK-NEXT: entry:
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