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[TII][NFC] Add renamable bit to copyPhysReg
The renamable flag is useful during MachineCopyPropagation but renamable flag will be dropped after lowerCopy. This patch add extra argument to pass the renamable flag to copyPhysReg.
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57 files changed

+122
-59
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1020,8 +1020,9 @@ class TargetInstrInfo : public MCInstrInfo {
10201020
/// large registers. See for example the ARM target.
10211021
virtual void copyPhysReg(MachineBasicBlock &MBB,
10221022
MachineBasicBlock::iterator MI, const DebugLoc &DL,
1023-
MCRegister DestReg, MCRegister SrcReg,
1024-
bool KillSrc) const {
1023+
MCRegister DestReg, MCRegister SrcReg, bool KillSrc,
1024+
bool RenamableDest = false,
1025+
bool RenamableSrc = false) const {
10251026
llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
10261027
}
10271028

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4851,7 +4851,9 @@ void AArch64InstrInfo::copyGPRRegTuple(MachineBasicBlock &MBB,
48514851
void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
48524852
MachineBasicBlock::iterator I,
48534853
const DebugLoc &DL, MCRegister DestReg,
4854-
MCRegister SrcReg, bool KillSrc) const {
4854+
MCRegister SrcReg, bool KillSrc,
4855+
bool RenamableDest,
4856+
bool RenamableSrc) const {
48554857
if (AArch64::GPR32spRegClass.contains(DestReg) &&
48564858
(AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
48574859
const TargetRegisterInfo *TRI = &getRegisterInfo();

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -344,7 +344,8 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
344344
llvm::ArrayRef<unsigned> Indices) const;
345345
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
346346
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
347-
bool KillSrc) const override;
347+
bool KillSrc, bool RenamableDest = false,
348+
bool RenamableSrc = false) const override;
348349

349350
void storeRegToStackSlot(MachineBasicBlock &MBB,
350351
MachineBasicBlock::iterator MBBI, Register SrcReg,

‎llvm/lib/Target/AMDGPU/R600InstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,8 @@ bool R600InstrInfo::isVector(const MachineInstr &MI) const {
4040
void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4141
MachineBasicBlock::iterator MI,
4242
const DebugLoc &DL, MCRegister DestReg,
43-
MCRegister SrcReg, bool KillSrc) const {
43+
MCRegister SrcReg, bool KillSrc,
44+
bool RenamableDest, bool RenamableSrc) const {
4445
unsigned VectorComponents = 0;
4546
if ((R600::R600_Reg128RegClass.contains(DestReg) ||
4647
R600::R600_Reg128VerticalRegClass.contains(DestReg)) &&

‎llvm/lib/Target/AMDGPU/R600InstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,7 +73,8 @@ class R600InstrInfo final : public R600GenInstrInfo {
7373

7474
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
7575
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
76-
bool KillSrc) const override;
76+
bool KillSrc, bool RenamableDest = false,
77+
bool RenamableSrc = false) const override;
7778
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
7879
MachineBasicBlock::iterator MBBI) const override;
7980

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -794,7 +794,8 @@ static void expandSGPRCopy(const SIInstrInfo &TII, MachineBasicBlock &MBB,
794794
void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
795795
MachineBasicBlock::iterator MI,
796796
const DebugLoc &DL, MCRegister DestReg,
797-
MCRegister SrcReg, bool KillSrc) const {
797+
MCRegister SrcReg, bool KillSrc,
798+
bool RenamableDest, bool RenamableSrc) const {
798799
const TargetRegisterClass *RC = RI.getPhysRegBaseClass(DestReg);
799800
unsigned Size = RI.getRegSizeInBits(*RC);
800801
const TargetRegisterClass *SrcRC = RI.getPhysRegBaseClass(SrcReg);

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -255,7 +255,8 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
255255

256256
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
257257
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
258-
bool KillSrc) const override;
258+
bool KillSrc, bool RenamableDest = false,
259+
bool RenamableSrc = false) const override;
259260

260261
void materializeImmediate(MachineBasicBlock &MBB,
261262
MachineBasicBlock::iterator MI, const DebugLoc &DL,

‎llvm/lib/Target/ARC/ARCInstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -281,7 +281,8 @@ unsigned ARCInstrInfo::removeBranch(MachineBasicBlock &MBB,
281281
void ARCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
282282
MachineBasicBlock::iterator I,
283283
const DebugLoc &DL, MCRegister DestReg,
284-
MCRegister SrcReg, bool KillSrc) const {
284+
MCRegister SrcReg, bool KillSrc,
285+
bool RenamableDest, bool RenamableSrc) const {
285286
assert(ARC::GPR32RegClass.contains(SrcReg) &&
286287
"Only GPR32 src copy supported.");
287288
assert(ARC::GPR32RegClass.contains(DestReg) &&

‎llvm/lib/Target/ARC/ARCInstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,8 @@ class ARCInstrInfo : public ARCGenInstrInfo {
6565

6666
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
6767
const DebugLoc &, MCRegister DestReg, MCRegister SrcReg,
68-
bool KillSrc) const override;
68+
bool KillSrc, bool RenamableDest = false,
69+
bool RenamableSrc = false) const override;
6970

7071
void storeRegToStackSlot(MachineBasicBlock &MBB,
7172
MachineBasicBlock::iterator MI, Register SrcReg,

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -892,7 +892,9 @@ void llvm::addPredicatedMveVpredROp(MachineInstrBuilder &MIB,
892892
void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
893893
MachineBasicBlock::iterator I,
894894
const DebugLoc &DL, MCRegister DestReg,
895-
MCRegister SrcReg, bool KillSrc) const {
895+
MCRegister SrcReg, bool KillSrc,
896+
bool RenamableDest,
897+
bool RenamableSrc) const {
896898
bool GPRDest = ARM::GPRRegClass.contains(DestReg);
897899
bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
898900

‎llvm/lib/Target/ARM/ARMBaseInstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -209,7 +209,8 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
209209

210210
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
211211
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
212-
bool KillSrc) const override;
212+
bool KillSrc, bool RenamableDest = false,
213+
bool RenamableSrc = false) const override;
213214

214215
void storeRegToStackSlot(MachineBasicBlock &MBB,
215216
MachineBasicBlock::iterator MBBI, Register SrcReg,

‎llvm/lib/Target/ARM/Thumb1InstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,8 @@ unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
4242
void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4343
MachineBasicBlock::iterator I,
4444
const DebugLoc &DL, MCRegister DestReg,
45-
MCRegister SrcReg, bool KillSrc) const {
45+
MCRegister SrcReg, bool KillSrc,
46+
bool RenamableDest, bool RenamableSrc) const {
4647
// Need to check the arch.
4748
MachineFunction &MF = *MBB.getParent();
4849
const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();

‎llvm/lib/Target/ARM/Thumb1InstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,8 @@ class Thumb1InstrInfo : public ARMBaseInstrInfo {
3939

4040
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
4141
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
42-
bool KillSrc) const override;
42+
bool KillSrc, bool RenamableDest = false,
43+
bool RenamableSrc = false) const override;
4344
void storeRegToStackSlot(MachineBasicBlock &MBB,
4445
MachineBasicBlock::iterator MBBI, Register SrcReg,
4546
bool isKill, int FrameIndex,

‎llvm/lib/Target/ARM/Thumb2InstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,8 @@ Thumb2InstrInfo::optimizeSelect(MachineInstr &MI,
151151
void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
152152
MachineBasicBlock::iterator I,
153153
const DebugLoc &DL, MCRegister DestReg,
154-
MCRegister SrcReg, bool KillSrc) const {
154+
MCRegister SrcReg, bool KillSrc,
155+
bool RenamableDest, bool RenamableSrc) const {
155156
// Handle SPR, DPR, and QPR copies.
156157
if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
157158
return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);

‎llvm/lib/Target/ARM/Thumb2InstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,8 @@ class Thumb2InstrInfo : public ARMBaseInstrInfo {
3939

4040
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
4141
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
42-
bool KillSrc) const override;
42+
bool KillSrc, bool RenamableDest = false,
43+
bool RenamableSrc = false) const override;
4344

4445
void storeRegToStackSlot(MachineBasicBlock &MBB,
4546
MachineBasicBlock::iterator MBBI, Register SrcReg,

‎llvm/lib/Target/AVR/AVRInstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,8 @@ AVRInstrInfo::AVRInstrInfo(AVRSubtarget &STI)
4242
void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4343
MachineBasicBlock::iterator MI,
4444
const DebugLoc &DL, MCRegister DestReg,
45-
MCRegister SrcReg, bool KillSrc) const {
45+
MCRegister SrcReg, bool KillSrc,
46+
bool RenamableDest, bool RenamableSrc) const {
4647
const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
4748
unsigned Opc;
4849

‎llvm/lib/Target/AVR/AVRInstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,8 @@ class AVRInstrInfo : public AVRGenInstrInfo {
7575

7676
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
7777
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
78-
bool KillSrc) const override;
78+
bool KillSrc, bool RenamableDest = false,
79+
bool RenamableSrc = false) const override;
7980
void storeRegToStackSlot(MachineBasicBlock &MBB,
8081
MachineBasicBlock::iterator MI, Register SrcReg,
8182
bool isKill, int FrameIndex,

‎llvm/lib/Target/BPF/BPFInstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,8 @@ BPFInstrInfo::BPFInstrInfo()
3131
void BPFInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3232
MachineBasicBlock::iterator I,
3333
const DebugLoc &DL, MCRegister DestReg,
34-
MCRegister SrcReg, bool KillSrc) const {
34+
MCRegister SrcReg, bool KillSrc,
35+
bool RenamableDest, bool RenamableSrc) const {
3536
if (BPF::GPRRegClass.contains(DestReg, SrcReg))
3637
BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
3738
.addReg(SrcReg, getKillRegState(KillSrc));

‎llvm/lib/Target/BPF/BPFInstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,8 @@ class BPFInstrInfo : public BPFGenInstrInfo {
3131

3232
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
3333
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
34-
bool KillSrc) const override;
34+
bool KillSrc, bool RenamableDest = false,
35+
bool RenamableSrc = false) const override;
3536

3637
bool expandPostRAPseudo(MachineInstr &MI) const override;
3738

‎llvm/lib/Target/CSKY/CSKYInstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -478,7 +478,8 @@ void CSKYInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
478478
void CSKYInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
479479
MachineBasicBlock::iterator I,
480480
const DebugLoc &DL, MCRegister DestReg,
481-
MCRegister SrcReg, bool KillSrc) const {
481+
MCRegister SrcReg, bool KillSrc,
482+
bool RenamableDest, bool RenamableSrc) const {
482483
if (CSKY::GPRRegClass.contains(SrcReg) &&
483484
CSKY::CARRYRegClass.contains(DestReg)) {
484485
if (STI.hasE2()) {

‎llvm/lib/Target/CSKY/CSKYInstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,8 @@ class CSKYInstrInfo : public CSKYGenInstrInfo {
5555

5656
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
5757
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
58-
bool KillSrc) const override;
58+
bool KillSrc, bool RenamableDest = false,
59+
bool RenamableSrc = false) const override;
5960

6061
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
6162
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,

‎llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -857,7 +857,9 @@ static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
857857
void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
858858
MachineBasicBlock::iterator I,
859859
const DebugLoc &DL, MCRegister DestReg,
860-
MCRegister SrcReg, bool KillSrc) const {
860+
MCRegister SrcReg, bool KillSrc,
861+
bool RenamableDest,
862+
bool RenamableSrc) const {
861863
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
862864
unsigned KillFlag = getKillRegState(KillSrc);
863865

‎llvm/lib/Target/Hexagon/HexagonInstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,8 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
174174
/// large registers. See for example the ARM target.
175175
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
176176
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
177-
bool KillSrc) const override;
177+
bool KillSrc, bool RenamableDest = false,
178+
bool RenamableSrc = false) const override;
178179

179180
/// Store the specified register of the given register class to the specified
180181
/// stack frame index. The store instruction is to be added to the given

‎llvm/lib/Target/Lanai/LanaiInstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,8 @@ void LanaiInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3535
MachineBasicBlock::iterator Position,
3636
const DebugLoc &DL,
3737
MCRegister DestinationRegister,
38-
MCRegister SourceRegister,
39-
bool KillSource) const {
38+
MCRegister SourceRegister, bool KillSource,
39+
bool RenamableDest, bool RenamableSrc) const {
4040
if (!Lanai::GPRRegClass.contains(DestinationRegister, SourceRegister)) {
4141
llvm_unreachable("Impossible reg-to-reg copy");
4242
}

‎llvm/lib/Target/Lanai/LanaiInstrInfo.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,9 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {
4949

5050
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
5151
const DebugLoc &DL, MCRegister DestinationRegister,
52-
MCRegister SourceRegister, bool KillSource) const override;
52+
MCRegister SourceRegister, bool KillSource,
53+
bool RenamableDest = false,
54+
bool RenamableSrc = false) const override;
5355

5456
void storeRegToStackSlot(MachineBasicBlock &MBB,
5557
MachineBasicBlock::iterator Position,

‎llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,9 @@ MCInst LoongArchInstrInfo::getNop() const {
3939
void LoongArchInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4040
MachineBasicBlock::iterator MBBI,
4141
const DebugLoc &DL, MCRegister DstReg,
42-
MCRegister SrcReg, bool KillSrc) const {
42+
MCRegister SrcReg, bool KillSrc,
43+
bool RenamableDest,
44+
bool RenamableSrc) const {
4345
if (LoongArch::GPRRegClass.contains(DstReg, SrcReg)) {
4446
BuildMI(MBB, MBBI, DL, get(LoongArch::OR), DstReg)
4547
.addReg(SrcReg, getKillRegState(KillSrc))

‎llvm/lib/Target/LoongArch/LoongArchInstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,8 @@ class LoongArchInstrInfo : public LoongArchGenInstrInfo {
3131

3232
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
3333
const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg,
34-
bool KillSrc) const override;
34+
bool KillSrc, bool RenamableDest = false,
35+
bool RenamableSrc = false) const override;
3536

3637
void storeRegToStackSlot(MachineBasicBlock &MBB,
3738
MachineBasicBlock::iterator MBBI, Register SrcReg,

‎llvm/lib/Target/M68k/M68kInstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -663,7 +663,8 @@ bool M68kInstrInfo::isPCRelRegisterOperandLegal(
663663
void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
664664
MachineBasicBlock::iterator MI,
665665
const DebugLoc &DL, MCRegister DstReg,
666-
MCRegister SrcReg, bool KillSrc) const {
666+
MCRegister SrcReg, bool KillSrc,
667+
bool RenamableDest, bool RenamableSrc) const {
667668
unsigned Opc = 0;
668669

669670
// First deal with the normal symmetric copies.

‎llvm/lib/Target/M68k/M68kInstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -271,7 +271,8 @@ class M68kInstrInfo : public M68kGenInstrInfo {
271271

272272
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
273273
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
274-
bool KillSrc) const override;
274+
bool KillSrc, bool RenamableDest = false,
275+
bool RenamableSrc = false) const override;
275276

276277
bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
277278
unsigned &Size, unsigned &Offset,

‎llvm/lib/Target/MSP430/MSP430InstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,8 @@ void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
9090
void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
9191
MachineBasicBlock::iterator I,
9292
const DebugLoc &DL, MCRegister DestReg,
93-
MCRegister SrcReg, bool KillSrc) const {
93+
MCRegister SrcReg, bool KillSrc,
94+
bool RenamableDest, bool RenamableSrc) const {
9495
unsigned Opc;
9596
if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
9697
Opc = MSP430::MOV16rr;

‎llvm/lib/Target/MSP430/MSP430InstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,8 @@ class MSP430InstrInfo : public MSP430GenInstrInfo {
3737

3838
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
3939
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
40-
bool KillSrc) const override;
40+
bool KillSrc, bool RenamableDest = false,
41+
bool RenamableSrc = false) const override;
4142

4243
void storeRegToStackSlot(MachineBasicBlock &MBB,
4344
MachineBasicBlock::iterator MI, Register SrcReg,

‎llvm/lib/Target/Mips/Mips16InstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,8 @@ Register Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
6969
void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
7070
MachineBasicBlock::iterator I,
7171
const DebugLoc &DL, MCRegister DestReg,
72-
MCRegister SrcReg, bool KillSrc) const {
72+
MCRegister SrcReg, bool KillSrc,
73+
bool RenamableDest, bool RenamableSrc) const {
7374
unsigned Opc = 0;
7475

7576
if (Mips::CPU16RegsRegClass.contains(DestReg) &&

‎llvm/lib/Target/Mips/Mips16InstrInfo.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,8 @@ class Mips16InstrInfo : public MipsInstrInfo {
5050

5151
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
5252
const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
53-
bool KillSrc) const override;
53+
bool KillSrc, bool RenamableDest = false,
54+
bool RenamableSrc = false) const override;
5455

5556
void storeRegToStack(MachineBasicBlock &MBB,
5657
MachineBasicBlock::iterator MBBI,

‎llvm/lib/Target/Mips/MipsSEInstrInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,8 @@ Register MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
8383
void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
8484
MachineBasicBlock::iterator I,
8585
const DebugLoc &DL, MCRegister DestReg,
86-
MCRegister SrcReg, bool KillSrc) const {
86+
MCRegister SrcReg, bool KillSrc,
87+
bool RenamableDest, bool RenamableSrc) const {
8788
unsigned Opc = 0, ZeroReg = 0;
8889
bool isMicroMips = Subtarget.inMicroMipsMode();
8990

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