Format and clean code

Created using spr 1.3.6-beta.1

Author: wangpc-pp

llvm/lib/Target/RISCV/RISCVFoldMasks.cpp

@@ -50,7 +50,7 @@ class RISCVFoldMasks : public MachineFunctionPass {
   bool convertToUnmasked(MachineInstr &MI) const;
   bool convertVMergeToVMv(MachineInstr &MI) const;
 
-  bool isAllOnesMask(const MachineOperand& MaskOp) const;
+  bool isAllOnesMask(const MachineOperand &MaskOp) const;
 };
 
 } // namespace

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -3425,8 +3425,7 @@ static bool usesAllOnesMask(SDValue MaskOp) {
   // TODO: Check that the VMSET is the expected bitwidth? The pseudo has
   // undefined behaviour if it's the wrong bitwidth, so we could choose to
   // assume that it's all-ones? Same applies to its VL.
-  return MaskOp->isMachineOpcode() &&
-         IsVMSet(MaskOp.getMachineOpcode());
+  return MaskOp->isMachineOpcode() && IsVMSet(MaskOp.getMachineOpcode());
 }
 
 // Return true if we can make sure mask of N is all-ones mask.
@@ -3477,11 +3476,6 @@ bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(MachineSDNode *N) {
     Ops.push_back(Op);
   }
 
-  // // Transitively apply any node glued to our new node.
-  // const auto *Glued = N->getGluedNode();
-  // if (auto *TGlued = Glued->getGluedNode())
-  //   Ops.push_back(SDValue(TGlued, TGlued->getNumValues() - 1));
-
   MachineSDNode *Result =
       CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);