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[LoongArch] Add some binary IR instructions testcases for LSX (#73929)
The IR instructions include: - Binary Operations: add fadd sub fsub mul fmul udiv sdiv fdiv - Bitwise Binary Operations: shl lshr ashr
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‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll

Lines changed: 122 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @add_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: add_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vadd.b $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = load <16 x i8>, ptr %a1
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%v2 = add <16 x i8> %v0, %v1
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store <16 x i8> %v2, ptr %res
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ret void
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}
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define void @add_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: add_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vadd.h $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = load <8 x i16>, ptr %a1
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%v2 = add <8 x i16> %v0, %v1
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store <8 x i16> %v2, ptr %res
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ret void
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}
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define void @add_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: add_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vadd.w $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = load <4 x i32>, ptr %a1
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%v2 = add <4 x i32> %v0, %v1
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store <4 x i32> %v2, ptr %res
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ret void
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}
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define void @add_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: add_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vadd.d $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = load <2 x i64>, ptr %a1
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%v2 = add <2 x i64> %v0, %v1
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store <2 x i64> %v2, ptr %res
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ret void
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}
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define void @add_v16i8_31(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: add_v16i8_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vaddi.bu $vr0, $vr0, 31
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = add <16 x i8> %v0, <i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31, i8 31>
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store <16 x i8> %v1, ptr %res
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ret void
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}
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define void @add_v8i16_31(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: add_v8i16_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vaddi.hu $vr0, $vr0, 31
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = add <8 x i16> %v0, <i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31, i16 31>
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store <8 x i16> %v1, ptr %res
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ret void
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}
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define void @add_v4i32_31(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: add_v4i32_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vaddi.wu $vr0, $vr0, 31
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = add <4 x i32> %v0, <i32 31, i32 31, i32 31, i32 31>
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store <4 x i32> %v1, ptr %res
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ret void
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}
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define void @add_v2i64_31(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: add_v2i64_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vaddi.du $vr0, $vr0, 31
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = add <2 x i64> %v0, <i64 31, i64 31>
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store <2 x i64> %v1, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/ashr.ll

Lines changed: 178 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @ashr_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: ashr_v16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vsra.b $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = load <16 x i8>, ptr %a1
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%v2 = ashr <16 x i8> %v0, %v1
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store <16 x i8> %v2, ptr %res
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ret void
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}
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define void @ashr_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: ashr_v8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vsra.h $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = load <8 x i16>, ptr %a1
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%v2 = ashr <8 x i16> %v0, %v1
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store <8 x i16> %v2, ptr %res
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ret void
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}
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define void @ashr_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: ashr_v4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vsra.w $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = load <4 x i32>, ptr %a1
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%v2 = ashr <4 x i32> %v0, %v1
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store <4 x i32> %v2, ptr %res
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ret void
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}
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define void @ashr_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
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; CHECK-LABEL: ashr_v2i64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vsra.d $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = load <2 x i64>, ptr %a1
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%v2 = ashr <2 x i64> %v0, %v1
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store <2 x i64> %v2, ptr %res
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ret void
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}
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define void @ashr_v16i8_1(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: ashr_v16i8_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsrai.b $vr0, $vr0, 1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = ashr <16 x i8> %v0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
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store <16 x i8> %v1, ptr %res
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ret void
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}
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define void @ashr_v16i8_7(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: ashr_v16i8_7:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsrai.b $vr0, $vr0, 7
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <16 x i8>, ptr %a0
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%v1 = ashr <16 x i8> %v0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
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store <16 x i8> %v1, ptr %res
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ret void
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}
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define void @ashr_v8i16_1(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: ashr_v8i16_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsrai.h $vr0, $vr0, 1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = ashr <8 x i16> %v0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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store <8 x i16> %v1, ptr %res
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ret void
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}
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define void @ashr_v8i16_15(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: ashr_v8i16_15:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsrai.h $vr0, $vr0, 15
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <8 x i16>, ptr %a0
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%v1 = ashr <8 x i16> %v0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
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store <8 x i16> %v1, ptr %res
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ret void
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}
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define void @ashr_v4i32_1(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: ashr_v4i32_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsrai.w $vr0, $vr0, 1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = ashr <4 x i32> %v0, <i32 1, i32 1, i32 1, i32 1>
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store <4 x i32> %v1, ptr %res
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ret void
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}
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define void @ashr_v4i32_31(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: ashr_v4i32_31:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsrai.w $vr0, $vr0, 31
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x i32>, ptr %a0
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%v1 = ashr <4 x i32> %v0, <i32 31, i32 31, i32 31, i32 31>
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store <4 x i32> %v1, ptr %res
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ret void
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}
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define void @ashr_v2i64_1(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: ashr_v2i64_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsrai.d $vr0, $vr0, 1
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = ashr <2 x i64> %v0, <i64 1, i64 1>
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store <2 x i64> %v1, ptr %res
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ret void
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}
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define void @ashr_v2i64_63(ptr %res, ptr %a0) nounwind {
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; CHECK-LABEL: ashr_v2i64_63:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a1, 0
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; CHECK-NEXT: vsrai.d $vr0, $vr0, 63
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x i64>, ptr %a0
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%v1 = ashr <2 x i64> %v0, <i64 63, i64 63>
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store <2 x i64> %v1, ptr %res
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ret void
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}

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fadd.ll

Lines changed: 34 additions & 0 deletions
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@@ -0,0 +1,34 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
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define void @fadd_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {
5+
; CHECK-LABEL: fadd_v4f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vfadd.s $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <4 x float>, ptr %a0
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%v1 = load <4 x float>, ptr %a1
15+
%v2 = fadd <4 x float> %v0, %v1
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store <4 x float> %v2, ptr %res
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ret void
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}
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define void @fadd_v2f64(ptr %res, ptr %a0, ptr %a1) nounwind {
21+
; CHECK-LABEL: fadd_v2f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vfadd.d $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
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%v0 = load <2 x double>, ptr %a0
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%v1 = load <2 x double>, ptr %a1
31+
%v2 = fadd <2 x double> %v0, %v1
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store <2 x double> %v2, ptr %res
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ret void
34+
}

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fdiv.ll

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
3+
4+
define void @fdiv_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {
5+
; CHECK-LABEL: fdiv_v4f32:
6+
; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vfdiv.s $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
13+
%v0 = load <4 x float>, ptr %a0
14+
%v1 = load <4 x float>, ptr %a1
15+
%v2 = fdiv <4 x float> %v0, %v1
16+
store <4 x float> %v2, ptr %res
17+
ret void
18+
}
19+
20+
define void @fdiv_v2f64(ptr %res, ptr %a0, ptr %a1) nounwind {
21+
; CHECK-LABEL: fdiv_v2f64:
22+
; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vld $vr0, $a2, 0
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; CHECK-NEXT: vld $vr1, $a1, 0
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; CHECK-NEXT: vfdiv.d $vr0, $vr1, $vr0
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; CHECK-NEXT: vst $vr0, $a0, 0
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; CHECK-NEXT: ret
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entry:
29+
%v0 = load <2 x double>, ptr %a0
30+
%v1 = load <2 x double>, ptr %a1
31+
%v2 = fdiv <2 x double> %v0, %v1
32+
store <2 x double> %v2, ptr %res
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ret void
34+
}

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