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[RISCV] Add test coverage for profitable vsetvli a0, zero, <vtype> cases
Test coverage for an upcoming change, we can avoid generating an immediate in register if we know the immediate is equal to vlmax.
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,3 +135,56 @@ define <6 x i1> @load_v6i1(ptr %p) {
135135
%x = load <6 x i1>, ptr %p
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ret <6 x i1> %x
137137
}
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define <4 x i32> @exact_vlen_i32_m1(ptr %p) vscale_range(2,2) {
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; CHECK-LABEL: exact_vlen_i32_m1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: ret
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%v = load <4 x i32>, ptr %p
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ret <4 x i32> %v
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}
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define <16 x i8> @exact_vlen_i8_m1(ptr %p) vscale_range(2,2) {
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; CHECK-LABEL: exact_vlen_i8_m1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: ret
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%v = load <16 x i8>, ptr %p
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ret <16 x i8> %v
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}
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define <32 x i8> @exact_vlen_i8_m2(ptr %p) vscale_range(2,2) {
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; CHECK-LABEL: exact_vlen_i8_m2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a1, 32
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; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: ret
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%v = load <32 x i8>, ptr %p
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ret <32 x i8> %v
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}
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define <128 x i8> @exact_vlen_i8_m8(ptr %p) vscale_range(2,2) {
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; CHECK-LABEL: exact_vlen_i8_m8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a1, 128
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; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: ret
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%v = load <128 x i8>, ptr %p
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ret <128 x i8> %v
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}
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define <16 x i64> @exact_vlen_i64_m8(ptr %p) vscale_range(2,2) {
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; CHECK-LABEL: exact_vlen_i64_m8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
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; CHECK-NEXT: vle64.v v8, (a0)
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; CHECK-NEXT: ret
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%v = load <16 x i64>, ptr %p
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ret <16 x i64> %v
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}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -237,6 +237,65 @@ define void @store_constant_v2i8_volatile(ptr %p) {
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store volatile <2 x i8> <i8 1, i8 1>, ptr %p
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ret void
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}
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define void @exact_vlen_i32_m1(ptr %p) vscale_range(2,2) {
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; CHECK-LABEL: exact_vlen_i32_m1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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store <4 x i32> zeroinitializer, ptr %p
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ret void
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}
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define void @exact_vlen_i8_m1(ptr %p) vscale_range(2,2) {
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; CHECK-LABEL: exact_vlen_i8_m1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
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store <16 x i8> zeroinitializer, ptr %p
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ret void
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}
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define void @exact_vlen_i8_m2(ptr %p) vscale_range(2,2) {
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; CHECK-LABEL: exact_vlen_i8_m2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a1, 32
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; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
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store <32 x i8> zeroinitializer, ptr %p
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ret void
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}
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define void @exact_vlen_i8_m8(ptr %p) vscale_range(2,2) {
277+
; CHECK-LABEL: exact_vlen_i8_m8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a1, 128
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; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
284+
store <128 x i8> zeroinitializer, ptr %p
285+
ret void
286+
}
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define void @exact_vlen_i64_m8(ptr %p) vscale_range(2,2) {
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; CHECK-LABEL: exact_vlen_i64_m8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: vse64.v v8, (a0)
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; CHECK-NEXT: ret
295+
store <16 x i64> zeroinitializer, ptr %p
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ret void
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}
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240299
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
241300
; RV32: {{.*}}
242301
; RV64: {{.*}}

‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -594,6 +594,40 @@ bb:
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ret i64 %tmp2
595595
}
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define void @add_v128i8(ptr %x, ptr %y) vscale_range(2,2) {
599+
; CHECK-LABEL: add_v128i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a2, 128
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; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma
603+
; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vle8.v v16, (a1)
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; CHECK-NEXT: vadd.vv v8, v8, v16
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
608+
%a = load <128 x i8>, ptr %x
609+
%b = load <128 x i8>, ptr %y
610+
%c = add <128 x i8> %a, %b
611+
store <128 x i8> %c, ptr %x
612+
ret void
613+
}
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615+
define void @add_v16i64(ptr %x, ptr %y) vscale_range(2,2) {
616+
; CHECK-LABEL: add_v16i64:
617+
; CHECK: # %bb.0:
618+
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
619+
; CHECK-NEXT: vle64.v v8, (a0)
620+
; CHECK-NEXT: vle64.v v16, (a1)
621+
; CHECK-NEXT: vadd.vv v8, v8, v16
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; CHECK-NEXT: vse64.v v8, (a0)
623+
; CHECK-NEXT: ret
624+
%a = load <16 x i64>, ptr %x
625+
%b = load <16 x i64>, ptr %y
626+
%c = add <16 x i64> %a, %b
627+
store <16 x i64> %c, ptr %x
628+
ret void
629+
}
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597631
declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
598632
<vscale x 1 x i64>,
599633
<vscale x 1 x i64>,

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