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[RISCV] Bump vector crypto to v1.0 RC2
Differential Revision: https://reviews.llvm.org/D158067
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‎clang/include/clang/Basic/riscv_vector.td

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2874,16 +2874,18 @@ multiclass RVVSignedWidenBinBuiltinSetVwsll
28742874
["vx", "Uw", "UwUvz"]]>;
28752875

28762876
let UnMaskedPolicyScheme = HasPassthruOperand in {
2877-
// zvbb
2877+
// zvkb
28782878
defm vandn : RVVUnsignedBinBuiltinSet;
2879-
defm vbrev : RVVOutBuiltinSetZvbb;
28802879
defm vbrev8 : RVVOutBuiltinSetZvbb;
28812880
defm vrev8 : RVVOutBuiltinSetZvbb;
2881+
defm vrol : RVVUnsignedShiftBuiltinSet;
2882+
defm vror : RVVUnsignedShiftBuiltinSet;
2883+
2884+
// zvbb
2885+
defm vbrev : RVVOutBuiltinSetZvbb;
28822886
defm vclz : RVVOutBuiltinSetZvbb;
28832887
defm vctz : RVVOutBuiltinSetZvbb;
28842888
defm vcpopv : RVVOutBuiltinSetZvbb;
2885-
defm vrol : RVVUnsignedShiftBuiltinSet;
2886-
defm vror : RVVUnsignedShiftBuiltinSet;
28872889
let OverloadedName = "vwsll" in
28882890
defm vwsll : RVVSignedWidenBinBuiltinSetVwsll;
28892891

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvl512b \
44
// RUN: -target-feature +experimental-zvbb \
55
// RUN: -target-feature +experimental-zvbc \
6+
// RUN: -target-feature +experimental-zvkb \
67
// RUN: -target-feature +experimental-zvkg \
78
// RUN: -target-feature +experimental-zvkned \
89
// RUN: -target-feature +experimental-zvknhb \

‎llvm/docs/RISCVUsage.rst

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -211,8 +211,8 @@ The primary goal of experimental support is to assist in the process of ratifica
211211
``experimental-ztso``
212212
LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`__ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware.
213213

214-
``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, ``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
215-
LLVM implements the `1.0.0-rc1 specification <https://github.com/riscv/riscv-crypto/releases/download/v20230620/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
214+
``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkb``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknc``, ``experimental-zvkned``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvks``, ``experimental-zvksc``, ``experimental-zvksed``, ``experimental-zvksg``, ``experimental-zvksh``, ``experimental-zvkt``
215+
LLVM implements the `1.0.0-rc2 specification <https://github.com/riscv/riscv-crypto/releases/download/v/riscv-crypto-spec-vector.pdf>`__. Note that current vector crypto extension version can be found in: <https://github.com/riscv/riscv-crypto>.
216216

217217
To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.
218218

‎llvm/include/llvm/IR/IntrinsicsRISCV.td

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1830,16 +1830,18 @@ def int_riscv_sm3p1 : ScalarCryptoGprIntrinsic32;
18301830
// These intrinsics will lower directly into the corresponding instructions
18311831
// added by the vector cyptography extension, if the extension is present.
18321832
let TargetPrefix = "riscv" in {
1833-
// Zvbb
1833+
// Zvkb
18341834
defm vandn : RISCVBinaryAAX;
1835-
defm vbrev : RISCVUnaryAA;
18361835
defm vbrev8 : RISCVUnaryAA;
18371836
defm vrev8 : RISCVUnaryAA;
1837+
defm vrol : RISCVBinaryAAX;
1838+
defm vror : RISCVBinaryAAX;
1839+
1840+
// Zvbb
1841+
defm vbrev : RISCVUnaryAA;
18381842
defm vclz : RISCVUnaryAA;
18391843
defm vctz : RISCVUnaryAA;
18401844
defm vcpopv : RISCVUnaryAA;
1841-
defm vrol : RISCVBinaryAAX;
1842-
defm vror : RISCVBinaryAAX;
18431845
defm vwsll : RISCVBinaryABX;
18441846

18451847
// Zvbc

‎llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -180,6 +180,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
180180
{"zvfbfwma", RISCVExtensionVersion{0, 8}},
181181

182182
// vector crypto
183+
{"zvkb", RISCVExtensionVersion{1, 0}},
183184
{"zvkg", RISCVExtensionVersion{1, 0}},
184185
{"zvkn", RISCVExtensionVersion{1, 0}},
185186
{"zvknc", RISCVExtensionVersion{1, 0}},
@@ -975,6 +976,7 @@ static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
975976
static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx",
976977
"zkne", "zknd", "zknh"};
977978
static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
979+
static const char *ImpliedExtsZvbb[] = {"zvkb"};
978980
static const char *ImpliedExtsZve32f[] = {"zve32x", "f"};
979981
static const char *ImpliedExtsZve32x[] = {"zvl32b", "zicsr"};
980982
static const char *ImpliedExtsZve64d[] = {"zve64f", "d"};
@@ -983,11 +985,11 @@ static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
983985
static const char *ImpliedExtsZvfbfmin[] = {"zve32f", "zfbfmin"};
984986
static const char *ImpliedExtsZvfbfwma[] = {"zvfbfmin"};
985987
static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
986-
static const char *ImpliedExtsZvkn[] = {"zvbb", "zvkned", "zvknhb", "zvkt"};
988+
static const char *ImpliedExtsZvkn[] = {"zvkb", "zvkned", "zvknhb", "zvkt"};
987989
static const char *ImpliedExtsZvknc[] = {"zvbc", "zvkn"};
988990
static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"};
989991
static const char *ImpliedExtsZvknhb[] = {"zvknha"};
990-
static const char *ImpliedExtsZvks[] = {"zvbb", "zvksed", "zvksh", "zvkt"};
992+
static const char *ImpliedExtsZvks[] = {"zvkb", "zvksed", "zvksh", "zvkt"};
991993
static const char *ImpliedExtsZvksc[] = {"zvbc", "zvks"};
992994
static const char *ImpliedExtsZvksg[] = {"zvkg", "zvks"};
993995
static const char *ImpliedExtsZvl1024b[] = {"zvl512b"};
@@ -1040,6 +1042,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
10401042
{{"zk"}, {ImpliedExtsZk}},
10411043
{{"zkn"}, {ImpliedExtsZkn}},
10421044
{{"zks"}, {ImpliedExtsZks}},
1045+
{{"zvbb"}, {ImpliedExtsZvbb}},
10431046
{{"zve32f"}, {ImpliedExtsZve32f}},
10441047
{{"zve32x"}, {ImpliedExtsZve32x}},
10451048
{{"zve64d"}, {ImpliedExtsZve64d}},

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -550,12 +550,20 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
550550
AssemblerPredicate<(all_of FeatureStdExtZawrs),
551551
"'Zawrs' (Wait on Reservation Set)">;
552552

553+
def FeatureStdExtZvkb
554+
: SubtargetFeature<"experimental-zvkb", "HasStdExtZvkb", "true",
555+
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
556+
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
557+
AssemblerPredicate<(all_of FeatureStdExtZvkb),
558+
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">;
559+
553560
def FeatureStdExtZvbb
554561
: SubtargetFeature<"experimental-zvbb", "HasStdExtZvbb", "true",
555-
"'Zvbb' (Vector Bit-manipulation used in Cryptography)">;
562+
"'Zvbb' (Vector basic bit-manipulation instructions.)",
563+
[FeatureStdExtZvkb]>;
556564
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
557565
AssemblerPredicate<(all_of FeatureStdExtZvbb),
558-
"'Zvbb' (Vector Bit-manipulation used in Cryptography)">;
566+
"'Zvbb' (Vector basic bit-manipulation instructions.)">;
559567

560568
def FeatureStdExtZvbc
561569
: SubtargetFeature<"experimental-zvbc", "HasStdExtZvbc", "true",
@@ -613,9 +621,9 @@ def FeatureStdExtZvkt
613621
def FeatureStdExtZvkn
614622
: SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true",
615623
"This extension is shorthand for the following set of "
616-
"other extensions: Zvkned, Zvknhb, Zvbb and Zvkt.",
624+
"other extensions: Zvkned, Zvknhb, Zvkb and Zvkt.",
617625
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
618-
FeatureStdExtZvbb, FeatureStdExtZvkt]>;
626+
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
619627

620628
def FeatureStdExtZvknc
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: SubtargetFeature<"experimental-zvknc", "HasStdExtZvknc", "true",
@@ -632,9 +640,9 @@ def FeatureStdExtZvkng
632640
def FeatureStdExtZvks
633641
: SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true",
634642
"This extension is shorthand for the following set of "
635-
"other extensions: Zvksed, Zvksh, Zvbb and Zvkt.",
643+
"other extensions: Zvksed, Zvksh, Zvkb and Zvkt.",
636644
[FeatureStdExtZvksed, FeatureStdExtZvksh,
637-
FeatureStdExtZvbb, FeatureStdExtZvkt]>;
645+
FeatureStdExtZvkb, FeatureStdExtZvkt]>;
638646

639647
def FeatureStdExtZvksc
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: SubtargetFeature<"experimental-zvksc", "HasStdExtZvksc", "true",

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