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-42
lines changed

4 files changed

+59
-42
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -468,8 +468,10 @@ class TargetLoweringBase {
468468
return true;
469469
}
470470

471-
/// Return true if the @llvm.experimental.get.alias.lane.mask intrinsic should be expanded using generic code in SelectionDAGBuilder.
472-
virtual bool shouldExpandGetAliasLaneMask(EVT VT, EVT PtrVT, unsigned EltSize) const {
471+
/// Return true if the @llvm.experimental.get.alias.lane.mask intrinsic should
472+
/// be expanded using generic code in SelectionDAGBuilder.
473+
virtual bool shouldExpandGetAliasLaneMask(EVT VT, EVT PtrVT,
474+
unsigned EltSize) const {
473475
return true;
474476
}
475477

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 20 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -8280,42 +8280,48 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
82808280
SDValue SourceValue = getValue(I.getOperand(0));
82818281
SDValue SinkValue = getValue(I.getOperand(1));
82828282
SDValue EltSize = getValue(I.getOperand(2));
8283-
bool IsWriteAfterRead = cast<ConstantSDNode>(getValue(I.getOperand(3)))->getZExtValue() != 0;
8283+
bool IsWriteAfterRead =
8284+
cast<ConstantSDNode>(getValue(I.getOperand(3)))->getZExtValue() != 0;
82848285
auto IntrinsicVT = EVT::getEVT(I.getType());
82858286
auto PtrVT = SourceValue->getValueType(0);
82868287

8287-
if (!TLI.shouldExpandGetAliasLaneMask(IntrinsicVT, PtrVT, cast<ConstantSDNode>(EltSize)->getSExtValue())) {
8288+
if (!TLI.shouldExpandGetAliasLaneMask(
8289+
IntrinsicVT, PtrVT,
8290+
cast<ConstantSDNode>(EltSize)->getSExtValue())) {
82888291
visitTargetIntrinsic(I, Intrinsic);
82898292
return;
82908293
}
82918294

8292-
SDValue Diff = DAG.getNode(ISD::SUB, sdl,
8293-
PtrVT, SinkValue, SourceValue);
8295+
SDValue Diff = DAG.getNode(ISD::SUB, sdl, PtrVT, SinkValue, SourceValue);
82948296
if (!IsWriteAfterRead)
82958297
Diff = DAG.getNode(ISD::ABS, sdl, PtrVT, Diff);
82968298

82978299
Diff = DAG.getNode(ISD::SDIV, sdl, PtrVT, Diff, EltSize);
82988300
SDValue Zero = DAG.getTargetConstant(0, sdl, PtrVT);
82998301

83008302
// If the difference is positive then some elements may alias
8301-
auto CmpVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
8302-
PtrVT);
8303-
SDValue Cmp = DAG.getSetCC(sdl, CmpVT, Diff, Zero, IsWriteAfterRead ? ISD::SETLE : ISD::SETEQ);
8303+
auto CmpVT =
8304+
TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), PtrVT);
8305+
SDValue Cmp = DAG.getSetCC(sdl, CmpVT, Diff, Zero,
8306+
IsWriteAfterRead ? ISD::SETLE : ISD::SETEQ);
83048307

83058308
// Splat the compare result then OR it with a lane mask
83068309
SDValue Splat = DAG.getSplat(IntrinsicVT, sdl, Cmp);
83078310

83088311
SDValue DiffMask;
83098312
// Don't emit an active lane mask if the target doesn't support it
83108313
if (TLI.shouldExpandGetActiveLaneMask(IntrinsicVT, PtrVT)) {
8311-
EVT VecTy = EVT::getVectorVT(*DAG.getContext(), PtrVT,
8312-
IntrinsicVT.getVectorElementCount());
8313-
SDValue DiffSplat = DAG.getSplat(VecTy, sdl, Diff);
8314-
SDValue VectorStep = DAG.getStepVector(sdl, VecTy);
8315-
DiffMask = DAG.getSetCC(sdl, IntrinsicVT, VectorStep,
8316-
DiffSplat, ISD::CondCode::SETULT);
8314+
EVT VecTy = EVT::getVectorVT(*DAG.getContext(), PtrVT,
8315+
IntrinsicVT.getVectorElementCount());
8316+
SDValue DiffSplat = DAG.getSplat(VecTy, sdl, Diff);
8317+
SDValue VectorStep = DAG.getStepVector(sdl, VecTy);
8318+
DiffMask = DAG.getSetCC(sdl, IntrinsicVT, VectorStep, DiffSplat,
8319+
ISD::CondCode::SETULT);
83178320
} else {
8318-
DiffMask = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, IntrinsicVT, DAG.getTargetConstant(Intrinsic::get_active_lane_mask, sdl, MVT::i64), Zero, Diff);
8321+
DiffMask = DAG.getNode(
8322+
ISD::INTRINSIC_WO_CHAIN, sdl, IntrinsicVT,
8323+
DAG.getTargetConstant(Intrinsic::get_active_lane_mask, sdl, MVT::i64),
8324+
Zero, Diff);
83198325
}
83208326
SDValue Or = DAG.getNode(ISD::OR, sdl, IntrinsicVT, DiffMask, Splat);
83218327
setValue(&I, Or);

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 33 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -2038,7 +2038,8 @@ bool AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,
20382038
return false;
20392039
}
20402040

2041-
bool AArch64TargetLowering::shouldExpandGetAliasLaneMask(EVT VT, EVT PtrVT, unsigned EltSize) const {
2041+
bool AArch64TargetLowering::shouldExpandGetAliasLaneMask(
2042+
EVT VT, EVT PtrVT, unsigned EltSize) const {
20422043
if (!Subtarget->hasSVE2())
20432044
return true;
20442045

@@ -2047,7 +2048,7 @@ bool AArch64TargetLowering::shouldExpandGetAliasLaneMask(EVT VT, EVT PtrVT, unsi
20472048

20482049
if (VT == MVT::v2i1 || VT == MVT::nxv2i1)
20492050
return EltSize != 8;
2050-
if( VT == MVT::v4i1 || VT == MVT::nxv4i1)
2051+
if (VT == MVT::v4i1 || VT == MVT::nxv4i1)
20512052
return EltSize != 4;
20522053
if (VT == MVT::v8i1 || VT == MVT::nxv8i1)
20532054
return EltSize != 2;
@@ -6040,12 +6041,14 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
60406041
case Intrinsic::aarch64_sve_whilewr_h:
60416042
case Intrinsic::aarch64_sve_whilewr_s:
60426043
case Intrinsic::aarch64_sve_whilewr_d:
6043-
return DAG.getNode(AArch64ISD::WHILEWR, dl, Op.getValueType(), Op.getOperand(1), Op.getOperand(2));
6044+
return DAG.getNode(AArch64ISD::WHILEWR, dl, Op.getValueType(),
6045+
Op.getOperand(1), Op.getOperand(2));
60446046
case Intrinsic::aarch64_sve_whilerw_b:
60456047
case Intrinsic::aarch64_sve_whilerw_h:
60466048
case Intrinsic::aarch64_sve_whilerw_s:
60476049
case Intrinsic::aarch64_sve_whilerw_d:
6048-
return DAG.getNode(AArch64ISD::WHILERW, dl, Op.getValueType(), Op.getOperand(1), Op.getOperand(2));
6050+
return DAG.getNode(AArch64ISD::WHILERW, dl, Op.getValueType(),
6051+
Op.getOperand(1), Op.getOperand(2));
60496052
case Intrinsic::aarch64_neon_abs: {
60506053
EVT Ty = Op.getValueType();
60516054
if (Ty == MVT::i64) {
@@ -6512,34 +6515,38 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
65126515
uint64_t EltSize = Op.getOperand(3)->getAsZExtVal();
65136516
bool IsWriteAfterRead = Op.getOperand(4)->getAsZExtVal() == 1;
65146517
switch (EltSize) {
6515-
case 1:
6516-
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_b : Intrinsic::aarch64_sve_whilerw_b;
6517-
break;
6518-
case 2:
6519-
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_h : Intrinsic::aarch64_sve_whilerw_h;
6520-
break;
6521-
case 4:
6522-
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_s : Intrinsic::aarch64_sve_whilerw_s;
6523-
break;
6524-
case 8:
6525-
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_d : Intrinsic::aarch64_sve_whilerw_d;
6526-
break;
6527-
default:
6528-
llvm_unreachable("Unexpected element size for get.alias.lane.mask");
6529-
break;
6518+
case 1:
6519+
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_b
6520+
: Intrinsic::aarch64_sve_whilerw_b;
6521+
break;
6522+
case 2:
6523+
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_h
6524+
: Intrinsic::aarch64_sve_whilerw_h;
6525+
break;
6526+
case 4:
6527+
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_s
6528+
: Intrinsic::aarch64_sve_whilerw_s;
6529+
break;
6530+
case 8:
6531+
IntrinsicID = IsWriteAfterRead ? Intrinsic::aarch64_sve_whilewr_d
6532+
: Intrinsic::aarch64_sve_whilerw_d;
6533+
break;
6534+
default:
6535+
llvm_unreachable("Unexpected element size for get.alias.lane.mask");
6536+
break;
65306537
}
65316538
}
6532-
SDValue ID =
6533-
DAG.getTargetConstant(IntrinsicID, dl, MVT::i64);
6539+
SDValue ID = DAG.getTargetConstant(IntrinsicID, dl, MVT::i64);
65346540

65356541
EVT VT = Op.getValueType();
65366542
if (VT.isScalableVector())
65376543
return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, ID, Op.getOperand(1),
65386544
Op.getOperand(2));
65396545

6540-
// We can use the SVE whilelo/whilewr/whilerw instruction to lower this intrinsic by
6541-
// creating the appropriate sequence of scalable vector operations and
6542-
// then extracting a fixed-width subvector from the scalable vector.
6546+
// We can use the SVE whilelo/whilewr/whilerw instruction to lower this
6547+
// intrinsic by creating the appropriate sequence of scalable vector
6548+
// operations and then extracting a fixed-width subvector from the scalable
6549+
// vector.
65436550

65446551
EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);
65456552
EVT WhileVT = ContainerVT.changeElementType(MVT::i1);
@@ -19927,7 +19934,8 @@ static bool isPredicateCCSettingOp(SDValue N) {
1992719934
// get_active_lane_mask is lowered to a whilelo instruction.
1992819935
N.getConstantOperandVal(0) == Intrinsic::get_active_lane_mask ||
1992919936
// get_alias_lane_mask is lowered to a whilewr/rw instruction.
19930-
N.getConstantOperandVal(0) == Intrinsic::experimental_get_alias_lane_mask)))
19937+
N.getConstantOperandVal(0) ==
19938+
Intrinsic::experimental_get_alias_lane_mask)))
1993119939
return true;
1993219940

1993319941
return false;

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -997,7 +997,8 @@ class AArch64TargetLowering : public TargetLowering {
997997

998998
bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const override;
999999

1000-
bool shouldExpandGetAliasLaneMask(EVT VT, EVT PtrVT, unsigned EltSize) const override;
1000+
bool shouldExpandGetAliasLaneMask(EVT VT, EVT PtrVT,
1001+
unsigned EltSize) const override;
10011002

10021003
bool
10031004
shouldExpandPartialReductionIntrinsic(const IntrinsicInst *I) const override;

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