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[RISCV] Adjust a few vector scheduler class names. NFC (#80795)
Shortening Iota to Iot seemed strange to me. I also remove the M from VMIota and VMIdx. The instruction for viota does have an m at the end of it, but vid.v does not. The M didn't seem very important for viota.
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‎llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -861,9 +861,9 @@ multiclass VMSFS_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
861861
SchedUnaryMC<"WriteVMSFSV", "ReadVMSFSV">;
862862
}
863863

864-
multiclass VMIOT_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
864+
multiclass VIOTA_MV_V<string opcodestr, bits<6> funct6, bits<5> vs1> {
865865
def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>,
866-
SchedUnaryMC<"WriteVMIotV", "ReadVMIotV">;
866+
SchedUnaryMC<"WriteVIotaV", "ReadVIotaV">;
867867
}
868868

869869
multiclass VSHT_IV_V_X_I<string opcodestr, bits<6> funct6> {
@@ -1621,7 +1621,7 @@ defm VMSIF_M : VMSFS_MV_V<"vmsif.m", 0b010100, 0b00011>;
16211621
// vmsof.m set-only-first mask bit
16221622
defm VMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010100, 0b00010>;
16231623
// Vector Iota Instruction
1624-
defm VIOTA_M : VMIOT_MV_V<"viota.m", 0b010100, 0b10000>;
1624+
defm VIOTA_M : VIOTA_MV_V<"viota.m", 0b010100, 0b10000>;
16251625

16261626
} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota
16271627

@@ -1631,7 +1631,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
16311631
let vs2 = 0 in
16321632
def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
16331633
(ins VMaskOp:$vm), "vid.v", "$vd$vm">,
1634-
SchedNullaryMC<"WriteVMIdxV">;
1634+
SchedNullaryMC<"WriteVIdxV">;
16351635

16361636
// Integer Scalar Move Instructions
16371637
let vm = 1, RVVConstraint = NoConstraint in {

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2066,10 +2066,10 @@ multiclass VPseudoVID_V {
20662066
defvar mx = m.MX;
20672067
let VLMul = m.value in {
20682068
def "_V_" # mx : VPseudoNullaryNoMask<m.vrclass>,
2069-
SchedNullary<"WriteVMIdxV", mx, forceMergeOpRead=true>;
2069+
SchedNullary<"WriteVIdxV", mx, forceMergeOpRead=true>;
20702070
def "_V_" # mx # "_MASK" : VPseudoNullaryMask<m.vrclass>,
20712071
RISCVMaskedPseudo<MaskIdx=1>,
2072-
SchedNullary<"WriteVMIdxV", mx,
2072+
SchedNullary<"WriteVIdxV", mx,
20732073
forceMergeOpRead=true>;
20742074
}
20752075
}
@@ -2084,17 +2084,17 @@ multiclass VPseudoNullaryPseudoM <string BaseInst> {
20842084
}
20852085
}
20862086

2087-
multiclass VPseudoVIOT_M {
2087+
multiclass VPseudoVIOTA_M {
20882088
defvar constraint = "@earlyclobber $rd";
20892089
foreach m = MxList in {
20902090
defvar mx = m.MX;
20912091
let VLMul = m.value in {
20922092
def "_" # mx : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
2093-
SchedUnary<"WriteVMIotV", "ReadVMIotV", mx,
2093+
SchedUnary<"WriteVIotaV", "ReadVIotaV", mx,
20942094
forceMergeOpRead=true>;
20952095
def "_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
20962096
RISCVMaskedPseudo<MaskIdx=2, MaskAffectsRes=true>,
2097-
SchedUnary<"WriteVMIotV", "ReadVMIotV", mx,
2097+
SchedUnary<"WriteVIotaV", "ReadVIotaV", mx,
20982098
forceMergeOpRead=true>;
20992099
}
21002100
}
@@ -6747,7 +6747,7 @@ defm PseudoVMSOF: VPseudoVSFS_M;
67476747
//===----------------------------------------------------------------------===//
67486748
// 15.8. Vector Iota Instruction
67496749
//===----------------------------------------------------------------------===//
6750-
defm PseudoVIOTA_M: VPseudoVIOT_M;
6750+
defm PseudoVIOTA_M: VPseudoVIOTA_M;
67516751

67526752
//===----------------------------------------------------------------------===//
67536753
// 15.9. Vector Element Index Instruction

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -868,8 +868,8 @@ foreach mx = SchedMxList in {
868868
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
869869
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
870870
let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
871-
defm "" : LMULWriteResMX<"WriteVMIotV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
872-
defm "" : LMULWriteResMX<"WriteVMIdxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
871+
defm "" : LMULWriteResMX<"WriteVIotaV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
872+
defm "" : LMULWriteResMX<"WriteVIdxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
873873
}
874874
}
875875

@@ -1173,7 +1173,7 @@ defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
11731173
defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
11741174
defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
11751175
defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
1176-
defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
1176+
defm "" : LMULReadAdvance<"ReadVIotaV", 0>;
11771177

11781178
// 17. Vector Permutation Instructions
11791179
def : ReadAdvance<ReadVIMovVX, 0>;

‎llvm/lib/Target/RISCV/RISCVScheduleV.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -473,9 +473,9 @@ defm "" : LMULSchedWrites<"WriteVMFFSV">;
473473
// 15.6. Vector Set-only-First Mask Bit
474474
defm "" : LMULSchedWrites<"WriteVMSFSV">;
475475
// 15.8. Vector Iota Instruction
476-
defm "" : LMULSchedWrites<"WriteVMIotV">;
476+
defm "" : LMULSchedWrites<"WriteVIotaV">;
477477
// 15.9. Vector Element Index Instruction
478-
defm "" : LMULSchedWrites<"WriteVMIdxV">;
478+
defm "" : LMULSchedWrites<"WriteVIdxV">;
479479

480480
// 16. Vector Permutation Instructions
481481
// 16.1. Integer Scalar Move Instructions
@@ -700,7 +700,7 @@ defm "" : LMULSchedReads<"ReadVMFFSV">;
700700
// 15.6. Vector Set-only-First Mask Bit
701701
defm "" : LMULSchedReads<"ReadVMSFSV">;
702702
// 15.8. Vector Iota Instruction
703-
defm "" : LMULSchedReads<"ReadVMIotV">;
703+
defm "" : LMULSchedReads<"ReadVIotaV">;
704704

705705
// 16. Vector Permutation Instructions
706706
// 16.1. Integer Scalar Move Instructions
@@ -912,8 +912,8 @@ defm "" : LMULWriteRes<"WriteVMALUV", []>;
912912
defm "" : LMULWriteRes<"WriteVMPopV", []>;
913913
defm "" : LMULWriteRes<"WriteVMFFSV", []>;
914914
defm "" : LMULWriteRes<"WriteVMSFSV", []>;
915-
defm "" : LMULWriteRes<"WriteVMIotV", []>;
916-
defm "" : LMULWriteRes<"WriteVMIdxV", []>;
915+
defm "" : LMULWriteRes<"WriteVIotaV", []>;
916+
defm "" : LMULWriteRes<"WriteVIdxV", []>;
917917

918918
// 16. Vector Permutation Instructions
919919
def : WriteRes<WriteVIMovVX, []>;
@@ -1074,7 +1074,7 @@ defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
10741074
defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
10751075
defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
10761076
defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
1077-
defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
1077+
defm "" : LMULReadAdvance<"ReadVIotaV", 0>;
10781078

10791079
// 16. Vector Permutation Instructions
10801080
def : ReadAdvance<ReadVIMovVX, 0>;

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