llvm
diff --git a/‎llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
Lines changed: 0 additions & 22 deletions b/‎llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll
Lines changed: 0 additions & 22 deletions
diff --git a/‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll renamed to ‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll renamed to ‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
diff --git a/‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll renamed to ‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll b/‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll renamed to ‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp-interleave.ll
diff --git a/‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll renamed to ‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll b/‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll renamed to ‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll
diff --git a/‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll renamed to ‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
Lines changed: 26 additions & 0 deletions b/‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll renamed to ‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int-interleave.ll
Lines changed: 26 additions & 0 deletions
diff --git a/‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll renamed to ‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll b/‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll renamed to ‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
@@ -683,6 +683,32 @@ define <4 x i8> @unary_interleave_10uu_v4i8(<4 x i8> %x) {
   ret <4 x i8> %a
 }
 
+define <16 x i16> @interleave_slp(<8 x i16> %v0, <8 x i16> %v1) {
+; V128-LABEL: interleave_slp:
+; V128:       # %bb.0: # %entry
+; V128-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; V128-NEXT:    vmv1r.v v10, v9
+; V128-NEXT:    vmv1r.v v11, v8
+; V128-NEXT:    vwaddu.vv v8, v11, v10
+; V128-NEXT:    li a0, -1
+; V128-NEXT:    vwmaccu.vx v8, a0, v10
+; V128-NEXT:    ret
+;
+; V512-LABEL: interleave_slp:
+; V512:       # %bb.0: # %entry
+; V512-NEXT:    vsetivli zero, 8, e16, mf4, ta, ma
+; V512-NEXT:    vwaddu.vv v10, v8, v9
+; V512-NEXT:    li a0, -1
+; V512-NEXT:    vwmaccu.vx v10, a0, v9
+; V512-NEXT:    vmv1r.v v8, v10
+; V512-NEXT:    ret
+entry:
+  %v2 = shufflevector <8 x i16> %v0, <8 x i16> poison, <16 x i32> <i32 0, i32 undef, i32 1, i32 undef, i32 2, i32 undef, i32 3, i32 undef, i32 4, i32 undef, i32 5, i32 undef, i32 6, i32 undef, i32 7, i32 undef>
+  %v3 = shufflevector <8 x i16> %v1, <8 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %v4 = shufflevector <16 x i16> %v2, <16 x i16> %v3, <16 x i32> <i32 0, i32 16, i32 2, i32 17, i32 4, i32 18, i32 6, i32 19, i32 8, i32 20, i32 10, i32 21, i32 12, i32 22, i32 14, i32 23>
+  ret <16 x i16> %v4
+}
+
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; RV32-V128: {{.*}}
 ; RV64-V128: {{.*}}