[RISCV][MC] Implement evaluateBranch for auipc+jalr pairs

This patch implements `MCInstrAnalysis` state in order to be able
analyze auipc+jalr pairs inside `evaluateBranch`.

This is implemented as follows:
- State: array of currently known GPR values;
- Whenever an auipc is detected in `updateState`, update the state value
  of RD with the immediate;
- Whenever a jalr is detected in `evaluateBranch`, check if the state
  holds a value for RS1 and use that to compute its target.

Note that this is similar to how binutils implements it and the output
of llvm-objdump should now mostly match the one of GNU objdump.

This patch also updates the relevant llvm-objdump patches and adds a new
one testing the output for interleaved auipc+jalr pairs.

Author: mtvec

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp

@@ -114,10 +114,40 @@ static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) {
 namespace {
 
 class RISCVMCInstrAnalysis : public MCInstrAnalysis {
+  std::optional<int64_t> GPRState[31];
+
+  void setGPRState(unsigned Reg, int64_t Value) {
+    assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && "Invalid GPR reg");
+
+    if (Reg != RISCV::X0)
+      GPRState[Reg - RISCV::X1] = Value;
+  }
+
+  std::optional<int64_t> getGPRState(unsigned Reg) const {
+    assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && "Invalid GPR reg");
+
+    if (Reg == RISCV::X0)
+      return 0;
+    return GPRState[Reg - RISCV::X1];
+  }
+
 public:
   explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
       : MCInstrAnalysis(Info) {}
 
+  void resetState() override {
+    std::fill(std::begin(GPRState), std::end(GPRState), std::nullopt);
+  }
+
+  void updateState(const MCInst &Inst, uint64_t Addr) override {
+    switch (Inst.getOpcode()) {
+    case RISCV::AUIPC:
+      setGPRState(Inst.getOperand(0).getReg(),
+                  Addr + (Inst.getOperand(1).getImm() << 12));
+      break;
+    }
+  }
+
   bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
                       uint64_t &Target) const override {
     if (isConditionalBranch(Inst)) {
@@ -140,6 +170,15 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
       return true;
     }
 
+    if (Inst.getOpcode() == RISCV::JALR) {
+      if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+        Target = *TargetRegState + Inst.getOperand(2).getImm();
+        return true;
+      }
+
+      return false;
+    }
+
     return false;
   }
 

llvm/test/tools/llvm-objdump/ELF/RISCV/branches.s

@@ -57,11 +57,11 @@ c.jal bar
 c.j bar
 
 # CHECK: auipc ra, 0
-# CHECK: jalr	ra, 16(ra){{$}}
+# CHECK: jalr	ra, 16(ra) <foo+0x58>
 call .Llocal
 
 # CHECK: auipc ra, 0
-# CHECK: jalr	ra, 16(ra){{$}}
+# CHECK: jalr	ra, 16(ra) <bar>
 call bar
 
 .Llocal:

llvm/test/tools/llvm-objdump/ELF/RISCV/multi-instr-target.s

@@ -0,0 +1,18 @@
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s | \
+# RUN:     llvm-objdump -d -M no-aliases --no-show-raw-insn - | \
+# RUN:     FileCheck %s
+
+## Test multiple interleaved auipc/jalr pairs
+# CHECK: auipc t0, 0
+1: auipc t0, %pcrel_hi(bar)
+# CHECK: auipc t1, 0
+2: auipc t1, %pcrel_hi(bar)
+# CHECK: jalr ra, 16(t0) <bar>
+jalr %pcrel_lo(1b)(t0)
+# CHECK: jalr ra, 12(t1) <bar>
+jalr %pcrel_lo(2b)(t1)
+
+# CHECK-LABEL: <bar>:
+bar:
+# CHECK: c.nop
+nop