Implement mffsl in pre-Power9 targets

ecnelises · ecnelises · commit 2c7688c2076c · 2023-10-10T12:10:27.000+08:00
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -152,7 +152,7 @@ TARGET_BUILTIN(__builtin_ppc_extract_sig, "ULLid", "", "power9-vector")
 BUILTIN(__builtin_ppc_mtfsb0, "vUIi", "")
 BUILTIN(__builtin_ppc_mtfsb1, "vUIi", "")
 BUILTIN(__builtin_ppc_mffs, "d", "")
-TARGET_BUILTIN(__builtin_ppc_mffsl, "d", "", "isa-v30-instructions")
+TARGET_BUILTIN(__builtin_ppc_mffsl, "d", "", "")
 BUILTIN(__builtin_ppc_mtfsf, "vUIiUi", "")
 BUILTIN(__builtin_ppc_mtfsfi, "vUIiUIi", "")
 BUILTIN(__builtin_ppc_set_fpscr_rn, "di", "")
diff --git a/clang/lib/Headers/ppc_wrappers/smmintrin.h b/clang/lib/Headers/ppc_wrappers/smmintrin.h
@@ -83,12 +83,7 @@ extern __inline __m128d
 
   switch (__rounding) {
   case _MM_FROUND_TO_NEAREST_INT:
-#ifdef _ARCH_PWR9
     __fpscr_save.__fr = __builtin_ppc_mffsl();
-#else
-    __fpscr_save.__fr = __builtin_ppc_mffs();
-    __fpscr_save.__fpscr &= 0x70007f0ffL;
-#endif
     __attribute__((fallthrough));
   case _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC:
     __builtin_ppc_set_fpscr_rn(0b00);
@@ -133,12 +128,7 @@ extern __inline __m128d
      */
     __asm__("" : : "wa"(__r));
     /* Restore enabled exceptions.  */
-#ifdef _ARCH_PWR9
     __fpscr_save.__fr = __builtin_ppc_mffsl();
-#else
-    __fpscr_save.__fr = __builtin_ppc_mffs();
-    __fpscr_save.__fpscr &= 0x70007f0ffL;
-#endif
     __fpscr_save.__fpscr |= __enables_save.__fpscr;
     __builtin_ppc_mtfsf(0b00000011, __fpscr_save.__fr);
   }
@@ -184,12 +174,7 @@ extern __inline __m128
 
   switch (__rounding) {
   case _MM_FROUND_TO_NEAREST_INT:
-#ifdef _ARCH_PWR9
     __fpscr_save.__fr = __builtin_ppc_mffsl();
-#else
-    __fpscr_save.__fr = __builtin_ppc_mffs();
-    __fpscr_save.__fpscr &= 0x70007f0ffL;
-#endif
     __attribute__((fallthrough));
   case _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC:
     __builtin_ppc_set_fpscr_rn(0b00);
@@ -234,12 +219,7 @@ extern __inline __m128
      */
     __asm__("" : : "wa"(__r));
     /* Restore enabled exceptions.  */
-#ifdef _ARCH_PWR9
     __fpscr_save.__fr = __builtin_ppc_mffsl();
-#else
-    __fpscr_save.__fr = __builtin_ppc_mffs();
-    __fpscr_save.__fpscr &= 0x70007f0ffL;
-#endif
     __fpscr_save.__fpscr |= __enables_save.__fpscr;
     __builtin_ppc_mtfsf(0b00000011, __fpscr_save.__fr);
   }
diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc.c b/clang/test/CodeGen/PowerPC/builtins-ppc.c
@@ -1,8 +1,6 @@
 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm %s -o - \
 // RUN:   | FileCheck %s
-// RUN: %clang_cc1 -triple powerpc-unknown-unknown -emit-llvm %s -o - \
-// RUN:   -target-cpu pwr9 | FileCheck %s --check-prefixes=P9,CHECK
 
 void test_eh_return_data_regno()
 {
@@ -45,10 +43,8 @@ void test_builtin_ppc_flm() {
   // CHECK: call double @llvm.ppc.setflm(double %2)
   res = __builtin_setflm(res);
 
-#ifdef _ARCH_PWR9
-  // P9: call double @llvm.ppc.mffsl()
+  // CHECK: call double @llvm.ppc.mffsl()
   res = __builtin_ppc_mffsl();
-#endif
 }
 
 double test_builtin_unpack_ldbl(long double x) {
diff --git a/clang/test/CodeGen/PowerPC/ppc-smmintrin.c b/clang/test/CodeGen/PowerPC/ppc-smmintrin.c
@@ -247,8 +247,7 @@ test_round() {
 // CHECK: call double @llvm.ppc.readflm()
 // CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
 // CHECK: %{{[0-9a-zA-Z_.]+}} = call <4 x float> asm "", "=^wa,0"
-// CHECK: call double @llvm.ppc.readflm()
-// P10: call double @llvm.ppc.mffsl()
+// CHECK: call double @llvm.ppc.mffsl()
 // CHECK: call double @llvm.ppc.setrnd(i32 0)
 // CHECK: %{{[0-9a-zA-Z_.]+}} = call <4 x float> asm "", "=^wa,0"
 // CHECK: call <4 x float> @vec_rint(float vector[4])
@@ -259,8 +258,7 @@ test_round() {
 // CHECK: call <4 x float> @vec_trunc(float vector[4])
 // CHECK: call <4 x float> @vec_rint(float vector[4])
 // CHECK: call void asm sideeffect "", "^wa"
-// CHECK: call double @llvm.ppc.readflm()
-// P10: call double @llvm.ppc.mffsl()
+// CHECK: call double @llvm.ppc.mffsl()
 // CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
 
 // CHECK-LABEL: define available_externally <4 x float> @_mm_round_ss(<4 x float> noundef %{{[0-9a-zA-Z_.]+}}, <4 x float> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
@@ -271,8 +269,7 @@ test_round() {
 // CHECK: call double @llvm.ppc.readflm()
 // CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
 // CHECK: %{{[0-9a-zA-Z_.]+}} = call <2 x double> asm "", "=^wa,0"
-// CHECK: call double @llvm.ppc.readflm()
-// P10: call double @llvm.ppc.mffsl()
+// CHECK: call double @llvm.ppc.mffsl()
 // CHECK: call double @llvm.ppc.setrnd(i32 0)
 // CHECK: %{{[0-9a-zA-Z_.]+}} = call <2 x double> asm "", "=^wa,0"
 // CHECK: call <2 x double> @vec_rint(double vector[2])
@@ -283,8 +280,7 @@ test_round() {
 // CHECK: call <2 x double> @vec_trunc(double vector[2])
 // CHECK: call <2 x double> @vec_rint(double vector[2])
 // CHECK: call void asm sideeffect "", "^wa"
-// CHECK: call double @llvm.ppc.readflm()
-// P10: call double @llvm.ppc.mffsl()
+// CHECK: call double @llvm.ppc.mffsl()
 // CHECK: call void @llvm.ppc.mtfsf(i32 3, double %{{[0-9a-zA-Z_.]+}})
 
 // CHECK-LABEL: define available_externally <2 x double> @_mm_round_sd(<2 x double> noundef %{{[0-9a-zA-Z_.]+}}, <2 x double> noundef %{{[0-9a-zA-Z_.]+}}, i32 noundef signext %{{[0-9a-zA-Z_.]+}})
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -646,8 +646,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f64, Custom);
 
-  // To handle counter-based loop conditions.
   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
+  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
 
   setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
   setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
@@ -11595,6 +11595,50 @@ SDValue PPCTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
   llvm_unreachable("ERROR:Should return for all cases within swtich.");
 }
 
+// Lower mffsl intrinsic with mffs in targets without ISA 3.0
+static SDValue lowerMFFSL(SDValue Op, SelectionDAG &DAG,
+                          const PPCSubtarget &Subtarget) {
+  assert(cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue() ==
+             Intrinsic::ppc_mffsl &&
+         "Should only be called on int_ppc_mffsl");
+  if (Subtarget.isISA3_0())
+    return Op;
+
+  SDLoc dl(Op);
+  SDValue Chain = Op.getOperand(0);
+  SDValue MFFS = DAG.getNode(PPCISD::MFFS, dl, {MVT::f64, MVT::Other}, Chain);
+  Chain = MFFS.getValue(1);
+
+  if (Subtarget.isPPC64()) {
+    SDValue Int = DAG.getNode(ISD::BITCAST, dl, MVT::i64, MFFS);
+    // Mask 29-31, 45-51 and 56-63 bits
+    SDValue Masked = DAG.getNode(ISD::AND, dl, MVT::i64, Int,
+                                 DAG.getConstant(0x70007f0ffULL, dl, MVT::i64));
+    SDValue Cast = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Masked);
+    return DAG.getMergeValues({Cast, Chain}, dl);
+  }
+
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachinePointerInfo PtrInfo;
+  int SSFI = MF.getFrameInfo().CreateStackObject(8, Align(8), false);
+  SDValue Base = DAG.getFrameIndex(SSFI, MVT::i32);
+  Chain = DAG.getStore(Chain, dl, MFFS, Base, PtrInfo);
+
+  assert(!Subtarget.isLittleEndian() && "32-bit little endian is unsupported!");
+  SDValue Offset4 = DAG.getNode(ISD::ADD, dl, MVT::i32, Base,
+                                DAG.getConstant(4, dl, MVT::i32));
+  SDValue Hi = DAG.getLoad(MVT::i32, dl, Chain, Base, PtrInfo);
+  SDValue Lo = DAG.getLoad(MVT::i32, dl, Hi.getValue(1), Offset4, PtrInfo);
+  Chain = Lo.getValue(1);
+  Hi =
+      DAG.getNode(ISD::AND, dl, MVT::i32, Hi, DAG.getConstant(7, dl, MVT::i32));
+  Lo = DAG.getNode(ISD::AND, dl, MVT::i32, Lo,
+                   DAG.getConstant(0x7f0ffULL, dl, MVT::i32));
+  Chain = DAG.getStore(Chain, dl, Hi, Base, PtrInfo);
+  Chain = DAG.getStore(Chain, dl, Lo, Offset4, PtrInfo);
+  return DAG.getLoad(MVT::f64, dl, Chain, Base, PtrInfo);
+}
+
 /// LowerOperation - Provide custom lowering hooks for some operations.
 ///
 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
@@ -11669,8 +11713,12 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
     return LowerFP_ROUND(Op, DAG);
   case ISD::ROTL:               return LowerROTL(Op, DAG);
 
-  // For counter-based loop handling.
-  case ISD::INTRINSIC_W_CHAIN:  return SDValue();
+  case ISD::INTRINSIC_W_CHAIN: {
+    if (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue() ==
+        Intrinsic::ppc_mffsl)
+      return lowerMFFSL(Op, DAG, Subtarget);
+    return SDValue();
+  }
 
   case ISD::BITCAST:            return LowerBITCAST(Op, DAG);
 
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3188,7 +3188,6 @@ def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm),
           (TCRETURNri CTRRC:$dst, imm:$imm)>;
 
 def : Pat<(int_ppc_readflm), (MFFS)>;
-def : Pat<(int_ppc_mffsl), (MFFSL)>;
 
 // Hi and Lo for Darwin Global Addresses.
 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
@@ -4510,6 +4509,9 @@ def : Pat<(int_ppc_dcbfl xoaddr:$dst),
 def : Pat<(int_ppc_dcbflp xoaddr:$dst),
           (DCBF 3, xoaddr:$dst)>;
 
+let Predicates = [IsISA3_0] in
+def : Pat<(int_ppc_mffsl), (MFFSL)>;
+
 let Predicates = [IsISA3_1] in {
   def DCBFPS  : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>;
   def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>;
diff --git a/llvm/test/CodeGen/PowerPC/read-set-flm.ll b/llvm/test/CodeGen/PowerPC/read-set-flm.ll
@@ -1,5 +1,8 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple powerpc64le-unknown-linux | FileCheck %s
+; RUN: llc < %s -mtriple powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s \
+; RUN:   --check-prefix=P9
+; RUN: llc < %s -mtriple powerpc64-ibm-aix | FileCheck %s --check-prefix=BE
+; RUN: llc < %s -mtriple powerpc-ibm-aix | FileCheck %s --check-prefix=BE32
 ; RUN: llc < %s -mtriple powerpc64le-unknown-linux -debug-only=machine-scheduler \
 ; RUN:   2>&1 | FileCheck %s --check-prefix=LOG
 ; REQUIRES: asserts
@@ -151,8 +154,47 @@ entry:
 define double @mffsl() {
 ; CHECK-LABEL: mffsl:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    mffsl 1
+; CHECK-NEXT:    mffs 0
+; CHECK-NEXT:    lis 4, -8192
+; CHECK-NEXT:    mffprd 3, 0
+; CHECK-NEXT:    ori 4, 4, 65055
+; CHECK-NEXT:    rldicl 4, 4, 3, 29
+; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    mtfprd 1, 3
 ; CHECK-NEXT:    blr
+;
+; P9-LABEL: mffsl:
+; P9:       # %bb.0: # %entry
+; P9-NEXT:    mffsl 1
+; P9-NEXT:    blr
+;
+; BE-LABEL: mffsl:
+; BE:       # %bb.0: # %entry
+; BE-NEXT:    mffs 0
+; BE-NEXT:    stfd 0, -16(1)
+; BE-NEXT:    ld 3, -16(1)
+; BE-NEXT:    lis 4, -8192
+; BE-NEXT:    ori 4, 4, 65055
+; BE-NEXT:    rldicl 4, 4, 3, 29
+; BE-NEXT:    and 3, 3, 4
+; BE-NEXT:    std 3, -8(1)
+; BE-NEXT:    lfd 1, -8(1)
+; BE-NEXT:    blr
+;
+; BE32-LABEL: mffsl:
+; BE32:       # %bb.0: # %entry
+; BE32-NEXT:    mffs 0
+; BE32-NEXT:    stfd 0, -8(1)
+; BE32-NEXT:    lis 4, 7
+; BE32-NEXT:    lwz 3, -4(1)
+; BE32-NEXT:    ori 4, 4, 61695
+; BE32-NEXT:    lwz 5, -8(1)
+; BE32-NEXT:    and 3, 3, 4
+; BE32-NEXT:    stw 3, -4(1)
+; BE32-NEXT:    clrlwi 3, 5, 29
+; BE32-NEXT:    stw 3, -8(1)
+; BE32-NEXT:    lfd 1, -8(1)
+; BE32-NEXT:    blr
 entry:
   %x = call double @llvm.ppc.mffsl()
   ret double %x
