Skip to content

Commit 2c9fb0a

Browse files
jiahanxie353jiahanxie353
committed
make some changes based on review
1 parent e6ef7ab commit 2c9fb0a

File tree

2 files changed

+50
-45
lines changed

2 files changed

+50
-45
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 50 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -68,6 +68,17 @@ typeIsLegalBoolVec(unsigned TypeIdx, std::initializer_list<LLT> BoolVecTys,
6868
return all(typeInSet(TypeIdx, BoolVecTys), P);
6969
}
7070

71+
static LegalityPredicate typeIsLegalPtrVec(unsigned TypeIdx,
72+
std::initializer_list<LLT> PtrVecTys,
73+
const RISCVSubtarget &ST) {
74+
LegalityPredicate P = [=, &ST](const LegalityQuery &Query) {
75+
return ST.hasVInstructions() &&
76+
(Query.Types[TypeIdx].getElementCount().getKnownMinValue() != 1 ||
77+
ST.getELen() == 64);
78+
};
79+
return all(typeInSet(TypeIdx, PtrVecTys), P);
80+
}
81+
7182
RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
7283
: STI(ST), XLen(STI.getXLen()), sXLen(LLT::scalar(XLen)) {
7384
const LLT sDoubleXLen = LLT::scalar(2 * XLen);
@@ -112,6 +123,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
112123
const LLT nxv4s64 = LLT::scalable_vector(4, s64);
113124
const LLT nxv8s64 = LLT::scalable_vector(8, s64);
114125

126+
const LLT nxv1p0 = LLT::scalable_vector(1, p0);
127+
const LLT nxv2p0 = LLT::scalable_vector(2, p0);
128+
const LLT nxv4p0 = LLT::scalable_vector(4, p0);
129+
const LLT nxv8p0 = LLT::scalable_vector(8, p0);
130+
115131
using namespace TargetOpcode;
116132

117133
auto BoolVecTys = {nxv1s1, nxv2s1, nxv4s1, nxv8s1, nxv16s1, nxv32s1, nxv64s1};
@@ -121,6 +137,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
121137
nxv32s16, nxv1s32, nxv2s32, nxv4s32, nxv8s32, nxv16s32,
122138
nxv1s64, nxv2s64, nxv4s64, nxv8s64};
123139

140+
auto PtrVecTys = {nxv1p0, nxv2p0, nxv4p0, nxv8p0};
141+
124142
getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
125143
.legalFor({s32, sXLen})
126144
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
@@ -261,27 +279,27 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
261279
.clampScalar(0, s32, (XLen == 64 || ST.hasStdExtD()) ? s64 : s32)
262280
.clampScalar(1, sXLen, sXLen);
263281

264-
auto &LoadStoreActions =
265-
getActionDefinitionsBuilder({G_LOAD, G_STORE})
266-
.legalForTypesWithMemDesc({{s32, p0, s8, 8},
267-
{s32, p0, s16, 16},
268-
{s32, p0, s32, 32},
269-
{p0, p0, sXLen, XLen},
270-
{nxv2s8, p0, nxv2s8, 8},
271-
{nxv4s8, p0, nxv4s8, 8},
272-
{nxv8s8, p0, nxv8s8, 8},
273-
{nxv16s8, p0, nxv16s8, 8},
274-
{nxv32s8, p0, nxv32s8, 8},
275-
{nxv64s8, p0, nxv64s8, 8},
276-
{nxv2s16, p0, nxv2s16, 16},
277-
{nxv4s16, p0, nxv4s16, 16},
278-
{nxv8s16, p0, nxv8s16, 16},
279-
{nxv16s16, p0, nxv16s16, 16},
280-
{nxv32s16, p0, nxv32s16, 16},
281-
{nxv2s32, p0, nxv2s32, 32},
282-
{nxv4s32, p0, nxv4s32, 32},
283-
{nxv8s32, p0, nxv8s32, 32},
284-
{nxv16s32, p0, nxv16s32, 32}});
282+
auto &LoadStoreActions = getActionDefinitionsBuilder({G_LOAD, G_STORE});
283+
if (ST.hasVInstructions())
284+
LoadStoreActions.legalForTypesWithMemDesc({{s32, p0, s8, 8},
285+
{s32, p0, s16, 16},
286+
{s32, p0, s32, 32},
287+
{p0, p0, sXLen, XLen},
288+
{nxv2s8, p0, nxv2s8, 8},
289+
{nxv4s8, p0, nxv4s8, 8},
290+
{nxv8s8, p0, nxv8s8, 8},
291+
{nxv16s8, p0, nxv16s8, 8},
292+
{nxv32s8, p0, nxv32s8, 8},
293+
{nxv64s8, p0, nxv64s8, 8},
294+
{nxv2s16, p0, nxv2s16, 16},
295+
{nxv4s16, p0, nxv4s16, 16},
296+
{nxv8s16, p0, nxv8s16, 16},
297+
{nxv16s16, p0, nxv16s16, 16},
298+
{nxv32s16, p0, nxv32s16, 16},
299+
{nxv2s32, p0, nxv2s32, 32},
300+
{nxv4s32, p0, nxv4s32, 32},
301+
{nxv8s32, p0, nxv8s32, 32},
302+
{nxv16s32, p0, nxv16s32, 32}});
285303

286304
auto &ExtLoadActions =
287305
getActionDefinitionsBuilder({G_SEXTLOAD, G_ZEXTLOAD})
@@ -309,10 +327,13 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
309327

310328
LoadStoreActions.widenScalarToNextPow2(0, /* MinSize = */ 8)
311329
.lowerIfMemSizeNotByteSizePow2()
312-
.customIf([=](const LegalityQuery &Query) {
313-
LLT Type = Query.Types[0];
314-
return Type.isScalableVector();
315-
})
330+
.customIf(all(LegalityPredicate([=](const LegalityQuery &Query) {
331+
LLT Type = Query.Types[0];
332+
return Type.isScalableVector();
333+
}),
334+
LegalityPredicate(LegalityPredicates::any(
335+
typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
336+
typeIsLegalPtrVec(0, PtrVecTys, ST)))))
316337
.clampScalar(0, s32, sXLen)
317338
.lower();
318339

@@ -690,28 +711,22 @@ bool RISCVLegalizerInfo::legalizeExt(MachineInstr &MI,
690711
bool RISCVLegalizerInfo::legalizeLoadStore(MachineInstr &MI,
691712
LegalizerHelper &Helper,
692713
MachineIRBuilder &MIB) const {
714+
assert((isa<GLoad>(MI) || isa<GStore>(MI)) &&
715+
"Machine instructions must be Load/Store.");
693716
MachineRegisterInfo &MRI = *MIB.getMRI();
694717
MachineFunction *MF = MI.getMF();
695718
const DataLayout &DL = MIB.getDataLayout();
696719
LLVMContext &Ctx = MF->getFunction().getContext();
697720

698721
Register DstReg = MI.getOperand(0).getReg();
699-
Register PtrReg = MI.getOperand(1).getReg();
700722
LLT DataTy = MRI.getType(DstReg);
701723
if (!DataTy.isVector())
702724
return false;
703725

704-
if (!(STI.hasVInstructions() &&
705-
(DataTy.getScalarSizeInBits() != 64 || STI.hasVInstructionsI64()) &&
706-
(DataTy.getElementCount().getKnownMinValue() != 1 ||
707-
STI.getELen() == 64)))
708-
return false;
709-
710726
if (!MI.hasOneMemOperand())
711727
return false;
712728

713729
MachineMemOperand *MMO = *MI.memoperands_begin();
714-
Align Alignment = MMO->getAlign();
715730

716731
const auto *TLI = STI.getTargetLowering();
717732
EVT VT = EVT::getEVT(getTypeForLLT(DataTy, Ctx));
@@ -728,17 +743,10 @@ bool RISCVLegalizerInfo::legalizeLoadStore(MachineInstr &MI,
728743
DataTy.getElementCount().getKnownMinValue() * (EltSizeBits / 8);
729744
LLT NewDataTy = LLT::scalable_vector(NumElements, 8);
730745

731-
MachinePointerInfo PI = MMO->getPointerInfo();
732-
MachineMemOperand *NewMMO =
733-
MF->getMachineMemOperand(PI, MMO->getFlags(), NewDataTy, Alignment);
734-
735-
if (isa<GLoad>(MI)) {
746+
if (isa<GLoad>(MI))
736747
Helper.bitcast(MI, 0, NewDataTy);
737-
} else {
738-
assert(isa<GStore>(MI) && "Machine instructions must be Load/Store.");
748+
else
739749
Helper.bitcast(MI, 0, NewDataTy);
740-
MIB.buildStore(MI.getOperand(0), PtrReg, *NewMMO);
741-
}
742750

743751
return true;
744752
}

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store.mir

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -728,7 +728,6 @@ body: |
728728
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8
729729
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 8 x s8>) = G_BITCAST [[COPY1]](<vscale x 4 x s16>)
730730
; CHECK-NEXT: G_STORE [[BITCAST]](<vscale x 8 x s8>), [[COPY]](p0) :: (store (<vscale x 8 x s8>) into %ir.pa, align 1)
731-
; CHECK-NEXT: G_STORE [[BITCAST]](<vscale x 8 x s8>), [[COPY]](p0) :: (store (<vscale x 8 x s8>) into %ir.pa, align 1)
732731
; CHECK-NEXT: PseudoRET
733732
%0:_(p0) = COPY $x10
734733
%1:_(<vscale x 4 x s16>) = COPY $v8
@@ -825,7 +824,6 @@ body: |
825824
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8
826825
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 8 x s8>) = G_BITCAST [[COPY1]](<vscale x 2 x s32>)
827826
; CHECK-NEXT: G_STORE [[BITCAST]](<vscale x 8 x s8>), [[COPY]](p0) :: (store (<vscale x 8 x s8>) into %ir.pa, align 2)
828-
; CHECK-NEXT: G_STORE [[BITCAST]](<vscale x 8 x s8>), [[COPY]](p0) :: (store (<vscale x 8 x s8>) into %ir.pa, align 2)
829827
; CHECK-NEXT: PseudoRET
830828
%0:_(p0) = COPY $x10
831829
%1:_(<vscale x 2 x s32>) = COPY $v8
@@ -922,7 +920,6 @@ body: |
922920
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2
923921
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 16 x s8>) = G_BITCAST [[COPY1]](<vscale x 2 x s64>)
924922
; CHECK-NEXT: G_STORE [[BITCAST]](<vscale x 16 x s8>), [[COPY]](p0) :: (store (<vscale x 16 x s8>) into %ir.pa, align 4)
925-
; CHECK-NEXT: G_STORE [[BITCAST]](<vscale x 16 x s8>), [[COPY]](p0) :: (store (<vscale x 16 x s8>) into %ir.pa, align 4)
926923
; CHECK-NEXT: PseudoRET
927924
%0:_(p0) = COPY $x10
928925
%1:_(<vscale x 2 x s64>) = COPY $v8m2

0 commit comments

Comments
 (0)