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[RISCV][SDAG] Improve codegen of select with constants if zicond is available
1 parent 8b8bdc6 commit 2cb0080

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2 files changed

+93
-112
lines changed

2 files changed

+93
-112
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7355,6 +7355,26 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
73557355
if (isNullConstant(TrueV))
73567356
return DAG.getNode(RISCVISD::CZERO_NEZ, DL, VT, FalseV, CondV);
73577357

7358+
// (select c, c1, c2) -> (add (czero_nez c2 - c1, c), c1)
7359+
// (select c, c1, c2) -> (add (czero_eqz c1 - c2, c), c2)
7360+
if (isa<ConstantSDNode>(TrueV) && isa<ConstantSDNode>(FalseV)) {
7361+
const APInt &TrueVal = TrueV->getAsAPIntVal();
7362+
const APInt &FalseVal = FalseV->getAsAPIntVal();
7363+
const int TrueValCost = RISCVMatInt::getIntMatCost(
7364+
TrueVal, Subtarget.getXLen(), Subtarget, /*CompressionCost=*/true);
7365+
const int FalseValCost = RISCVMatInt::getIntMatCost(
7366+
FalseVal, Subtarget.getXLen(), Subtarget, /*CompressionCost=*/true);
7367+
bool IsCZERO_NEZ = TrueValCost <= FalseValCost;
7368+
SDValue LHSVal = DAG.getConstant(
7369+
IsCZERO_NEZ ? FalseVal - TrueVal : TrueVal - FalseVal, DL, VT);
7370+
SDValue RHSVal =
7371+
DAG.getConstant(IsCZERO_NEZ ? TrueVal : FalseVal, DL, VT);
7372+
SDValue CMOV =
7373+
DAG.getNode(IsCZERO_NEZ ? RISCVISD::CZERO_NEZ : RISCVISD::CZERO_EQZ,
7374+
DL, VT, LHSVal, CondV);
7375+
return DAG.getNode(ISD::ADD, DL, VT, CMOV, RHSVal);
7376+
}
7377+
73587378
// (select c, (and f, x), f) -> (or (and f, x), (czero_nez f, c))
73597379
if (TrueV.getOpcode() == ISD::AND &&
73607380
(TrueV.getOperand(0) == FalseV || TrueV.getOperand(1) == FalseV))

‎llvm/test/CodeGen/RISCV/select.ll

Lines changed: 73 additions & 112 deletions
Original file line numberDiff line numberDiff line change
@@ -1473,20 +1473,16 @@ define i32 @select_cst1(i1 zeroext %cond) {
14731473
;
14741474
; RV64IMXVTCONDOPS-LABEL: select_cst1:
14751475
; RV64IMXVTCONDOPS: # %bb.0:
1476-
; RV64IMXVTCONDOPS-NEXT: li a1, 20
1477-
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a0
1478-
; RV64IMXVTCONDOPS-NEXT: li a2, 10
1479-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a2, a0
1480-
; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1
1476+
; RV64IMXVTCONDOPS-NEXT: li a1, 10
1477+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1478+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 10
14811479
; RV64IMXVTCONDOPS-NEXT: ret
14821480
;
14831481
; CHECKZICOND-LABEL: select_cst1:
14841482
; CHECKZICOND: # %bb.0:
1485-
; CHECKZICOND-NEXT: li a1, 20
1486-
; CHECKZICOND-NEXT: czero.nez a1, a1, a0
1487-
; CHECKZICOND-NEXT: li a2, 10
1488-
; CHECKZICOND-NEXT: czero.eqz a0, a2, a0
1489-
; CHECKZICOND-NEXT: or a0, a0, a1
1483+
; CHECKZICOND-NEXT: li a1, 10
1484+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
1485+
; CHECKZICOND-NEXT: addi a0, a0, 10
14901486
; CHECKZICOND-NEXT: ret
14911487
%ret = select i1 %cond, i32 10, i32 20
14921488
ret i32 %ret
@@ -1517,32 +1513,26 @@ define i32 @select_cst2(i1 zeroext %cond) {
15171513
;
15181514
; RV64IMXVTCONDOPS-LABEL: select_cst2:
15191515
; RV64IMXVTCONDOPS: # %bb.0:
1520-
; RV64IMXVTCONDOPS-NEXT: li a1, 10
1521-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0
1522-
; RV64IMXVTCONDOPS-NEXT: lui a2, 5
1523-
; RV64IMXVTCONDOPS-NEXT: addiw a2, a2, -480
1524-
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0
1525-
; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0
1516+
; RV64IMXVTCONDOPS-NEXT: lui a1, 5
1517+
; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -490
1518+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1519+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 10
15261520
; RV64IMXVTCONDOPS-NEXT: ret
15271521
;
15281522
; RV32IMZICOND-LABEL: select_cst2:
15291523
; RV32IMZICOND: # %bb.0:
1530-
; RV32IMZICOND-NEXT: li a1, 10
1531-
; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0
1532-
; RV32IMZICOND-NEXT: lui a2, 5
1533-
; RV32IMZICOND-NEXT: addi a2, a2, -480
1534-
; RV32IMZICOND-NEXT: czero.nez a0, a2, a0
1535-
; RV32IMZICOND-NEXT: or a0, a1, a0
1524+
; RV32IMZICOND-NEXT: lui a1, 5
1525+
; RV32IMZICOND-NEXT: addi a1, a1, -490
1526+
; RV32IMZICOND-NEXT: czero.nez a0, a1, a0
1527+
; RV32IMZICOND-NEXT: addi a0, a0, 10
15361528
; RV32IMZICOND-NEXT: ret
15371529
;
15381530
; RV64IMZICOND-LABEL: select_cst2:
15391531
; RV64IMZICOND: # %bb.0:
1540-
; RV64IMZICOND-NEXT: li a1, 10
1541-
; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0
1542-
; RV64IMZICOND-NEXT: lui a2, 5
1543-
; RV64IMZICOND-NEXT: addiw a2, a2, -480
1544-
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
1545-
; RV64IMZICOND-NEXT: or a0, a1, a0
1532+
; RV64IMZICOND-NEXT: lui a1, 5
1533+
; RV64IMZICOND-NEXT: addiw a1, a1, -490
1534+
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
1535+
; RV64IMZICOND-NEXT: addi a0, a0, 10
15461536
; RV64IMZICOND-NEXT: ret
15471537
%ret = select i1 %cond, i32 10, i32 20000
15481538
ret i32 %ret
@@ -1575,35 +1565,32 @@ define i32 @select_cst3(i1 zeroext %cond) {
15751565
;
15761566
; RV64IMXVTCONDOPS-LABEL: select_cst3:
15771567
; RV64IMXVTCONDOPS: # %bb.0:
1578-
; RV64IMXVTCONDOPS-NEXT: lui a1, 5
1579-
; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -480
1580-
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a0
1581-
; RV64IMXVTCONDOPS-NEXT: lui a2, 7
1582-
; RV64IMXVTCONDOPS-NEXT: addiw a2, a2, 1328
1583-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a2, a0
1584-
; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1
1568+
; RV64IMXVTCONDOPS-NEXT: lui a1, 1048574
1569+
; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -1808
1570+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1571+
; RV64IMXVTCONDOPS-NEXT: lui a1, 7
1572+
; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, 1328
1573+
; RV64IMXVTCONDOPS-NEXT: add a0, a0, a1
15851574
; RV64IMXVTCONDOPS-NEXT: ret
15861575
;
15871576
; RV32IMZICOND-LABEL: select_cst3:
15881577
; RV32IMZICOND: # %bb.0:
1589-
; RV32IMZICOND-NEXT: lui a1, 5
1590-
; RV32IMZICOND-NEXT: addi a1, a1, -480
1591-
; RV32IMZICOND-NEXT: czero.nez a1, a1, a0
1592-
; RV32IMZICOND-NEXT: lui a2, 7
1593-
; RV32IMZICOND-NEXT: addi a2, a2, 1328
1594-
; RV32IMZICOND-NEXT: czero.eqz a0, a2, a0
1595-
; RV32IMZICOND-NEXT: or a0, a0, a1
1578+
; RV32IMZICOND-NEXT: lui a1, 1048574
1579+
; RV32IMZICOND-NEXT: addi a1, a1, -1808
1580+
; RV32IMZICOND-NEXT: czero.nez a0, a1, a0
1581+
; RV32IMZICOND-NEXT: lui a1, 7
1582+
; RV32IMZICOND-NEXT: addi a1, a1, 1328
1583+
; RV32IMZICOND-NEXT: add a0, a0, a1
15961584
; RV32IMZICOND-NEXT: ret
15971585
;
15981586
; RV64IMZICOND-LABEL: select_cst3:
15991587
; RV64IMZICOND: # %bb.0:
1600-
; RV64IMZICOND-NEXT: lui a1, 5
1601-
; RV64IMZICOND-NEXT: addiw a1, a1, -480
1602-
; RV64IMZICOND-NEXT: czero.nez a1, a1, a0
1603-
; RV64IMZICOND-NEXT: lui a2, 7
1604-
; RV64IMZICOND-NEXT: addiw a2, a2, 1328
1605-
; RV64IMZICOND-NEXT: czero.eqz a0, a2, a0
1606-
; RV64IMZICOND-NEXT: or a0, a0, a1
1588+
; RV64IMZICOND-NEXT: lui a1, 1048574
1589+
; RV64IMZICOND-NEXT: addiw a1, a1, -1808
1590+
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
1591+
; RV64IMZICOND-NEXT: lui a1, 7
1592+
; RV64IMZICOND-NEXT: addiw a1, a1, 1328
1593+
; RV64IMZICOND-NEXT: add a0, a0, a1
16071594
; RV64IMZICOND-NEXT: ret
16081595
%ret = select i1 %cond, i32 30000, i32 20000
16091596
ret i32 %ret
@@ -1632,21 +1619,27 @@ define i32 @select_cst4(i1 zeroext %cond) {
16321619
;
16331620
; RV64IMXVTCONDOPS-LABEL: select_cst4:
16341621
; RV64IMXVTCONDOPS: # %bb.0:
1635-
; RV64IMXVTCONDOPS-NEXT: li a1, 2047
1636-
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a0
1637-
; RV64IMXVTCONDOPS-NEXT: li a2, -2048
1638-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a2, a0
1639-
; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1
1622+
; RV64IMXVTCONDOPS-NEXT: lui a1, 1
1623+
; RV64IMXVTCONDOPS-NEXT: addiw a1, a1, -1
1624+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1625+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, -2048
16401626
; RV64IMXVTCONDOPS-NEXT: ret
16411627
;
1642-
; CHECKZICOND-LABEL: select_cst4:
1643-
; CHECKZICOND: # %bb.0:
1644-
; CHECKZICOND-NEXT: li a1, 2047
1645-
; CHECKZICOND-NEXT: czero.nez a1, a1, a0
1646-
; CHECKZICOND-NEXT: li a2, -2048
1647-
; CHECKZICOND-NEXT: czero.eqz a0, a2, a0
1648-
; CHECKZICOND-NEXT: or a0, a0, a1
1649-
; CHECKZICOND-NEXT: ret
1628+
; RV32IMZICOND-LABEL: select_cst4:
1629+
; RV32IMZICOND: # %bb.0:
1630+
; RV32IMZICOND-NEXT: lui a1, 1
1631+
; RV32IMZICOND-NEXT: addi a1, a1, -1
1632+
; RV32IMZICOND-NEXT: czero.nez a0, a1, a0
1633+
; RV32IMZICOND-NEXT: addi a0, a0, -2048
1634+
; RV32IMZICOND-NEXT: ret
1635+
;
1636+
; RV64IMZICOND-LABEL: select_cst4:
1637+
; RV64IMZICOND: # %bb.0:
1638+
; RV64IMZICOND-NEXT: lui a1, 1
1639+
; RV64IMZICOND-NEXT: addiw a1, a1, -1
1640+
; RV64IMZICOND-NEXT: czero.nez a0, a1, a0
1641+
; RV64IMZICOND-NEXT: addi a0, a0, -2048
1642+
; RV64IMZICOND-NEXT: ret
16501643
%ret = select i1 %cond, i32 -2048, i32 2047
16511644
ret i32 %ret
16521645
}
@@ -1676,33 +1669,17 @@ define i32 @select_cst5(i1 zeroext %cond) {
16761669
;
16771670
; RV64IMXVTCONDOPS-LABEL: select_cst5:
16781671
; RV64IMXVTCONDOPS: # %bb.0:
1679-
; RV64IMXVTCONDOPS-NEXT: li a1, 2047
1680-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0
1681-
; RV64IMXVTCONDOPS-NEXT: lui a2, 1
1682-
; RV64IMXVTCONDOPS-NEXT: addiw a2, a2, -2047
1683-
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0
1684-
; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0
1672+
; RV64IMXVTCONDOPS-NEXT: li a1, 2
1673+
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a1, a0
1674+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 2047
16851675
; RV64IMXVTCONDOPS-NEXT: ret
16861676
;
1687-
; RV32IMZICOND-LABEL: select_cst5:
1688-
; RV32IMZICOND: # %bb.0:
1689-
; RV32IMZICOND-NEXT: li a1, 2047
1690-
; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0
1691-
; RV32IMZICOND-NEXT: lui a2, 1
1692-
; RV32IMZICOND-NEXT: addi a2, a2, -2047
1693-
; RV32IMZICOND-NEXT: czero.nez a0, a2, a0
1694-
; RV32IMZICOND-NEXT: or a0, a1, a0
1695-
; RV32IMZICOND-NEXT: ret
1696-
;
1697-
; RV64IMZICOND-LABEL: select_cst5:
1698-
; RV64IMZICOND: # %bb.0:
1699-
; RV64IMZICOND-NEXT: li a1, 2047
1700-
; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0
1701-
; RV64IMZICOND-NEXT: lui a2, 1
1702-
; RV64IMZICOND-NEXT: addiw a2, a2, -2047
1703-
; RV64IMZICOND-NEXT: czero.nez a0, a2, a0
1704-
; RV64IMZICOND-NEXT: or a0, a1, a0
1705-
; RV64IMZICOND-NEXT: ret
1677+
; CHECKZICOND-LABEL: select_cst5:
1678+
; CHECKZICOND: # %bb.0:
1679+
; CHECKZICOND-NEXT: li a1, 2
1680+
; CHECKZICOND-NEXT: czero.nez a0, a1, a0
1681+
; CHECKZICOND-NEXT: addi a0, a0, 2047
1682+
; CHECKZICOND-NEXT: ret
17061683
%ret = select i1 %cond, i32 2047, i32 2049
17071684
ret i32 %ret
17081685
}
@@ -1732,33 +1709,17 @@ define i32 @select_cst6(i1 zeroext %cond) {
17321709
;
17331710
; RV64IMXVTCONDOPS-LABEL: select_cst6:
17341711
; RV64IMXVTCONDOPS: # %bb.0:
1735-
; RV64IMXVTCONDOPS-NEXT: li a1, 2047
1736-
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a1, a1, a0
1737-
; RV64IMXVTCONDOPS-NEXT: lui a2, 1
1738-
; RV64IMXVTCONDOPS-NEXT: addiw a2, a2, -2047
1739-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a2, a0
1740-
; RV64IMXVTCONDOPS-NEXT: or a0, a0, a1
1712+
; RV64IMXVTCONDOPS-NEXT: li a1, 2
1713+
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0
1714+
; RV64IMXVTCONDOPS-NEXT: addi a0, a0, 2047
17411715
; RV64IMXVTCONDOPS-NEXT: ret
17421716
;
1743-
; RV32IMZICOND-LABEL: select_cst6:
1744-
; RV32IMZICOND: # %bb.0:
1745-
; RV32IMZICOND-NEXT: li a1, 2047
1746-
; RV32IMZICOND-NEXT: czero.nez a1, a1, a0
1747-
; RV32IMZICOND-NEXT: lui a2, 1
1748-
; RV32IMZICOND-NEXT: addi a2, a2, -2047
1749-
; RV32IMZICOND-NEXT: czero.eqz a0, a2, a0
1750-
; RV32IMZICOND-NEXT: or a0, a0, a1
1751-
; RV32IMZICOND-NEXT: ret
1752-
;
1753-
; RV64IMZICOND-LABEL: select_cst6:
1754-
; RV64IMZICOND: # %bb.0:
1755-
; RV64IMZICOND-NEXT: li a1, 2047
1756-
; RV64IMZICOND-NEXT: czero.nez a1, a1, a0
1757-
; RV64IMZICOND-NEXT: lui a2, 1
1758-
; RV64IMZICOND-NEXT: addiw a2, a2, -2047
1759-
; RV64IMZICOND-NEXT: czero.eqz a0, a2, a0
1760-
; RV64IMZICOND-NEXT: or a0, a0, a1
1761-
; RV64IMZICOND-NEXT: ret
1717+
; CHECKZICOND-LABEL: select_cst6:
1718+
; CHECKZICOND: # %bb.0:
1719+
; CHECKZICOND-NEXT: li a1, 2
1720+
; CHECKZICOND-NEXT: czero.eqz a0, a1, a0
1721+
; CHECKZICOND-NEXT: addi a0, a0, 2047
1722+
; CHECKZICOND-NEXT: ret
17621723
%ret = select i1 %cond, i32 2049, i32 2047
17631724
ret i32 %ret
17641725
}

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