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davemgreendavemgreen
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[AArch64] Add some tests for csel/subs with swapped conditions. NFC
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‎llvm/test/CodeGen/AArch64/csel-subs-swapped.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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define i32 @eq_i32(i32 %x) {
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; CHECK-LABEL: eq_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
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; CHECK-NEXT: cmn w0, #512, lsl #12 // =2097152
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; CHECK-NEXT: sub w8, w8, w0
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; CHECK-NEXT: csel w0, w0, w8, eq
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; CHECK-NEXT: ret
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%cmp = icmp eq i32 %x, -2097152
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%sub = sub i32 -2097152, %x
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%retval.0 = select i1 %cmp, i32 %x, i32 %sub
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ret i32 %retval.0
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}
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define i32 @ne_i32(i32 %x) {
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; CHECK-LABEL: ne_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
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; CHECK-NEXT: cmn w0, #512, lsl #12 // =2097152
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; CHECK-NEXT: sub w8, w8, w0
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; CHECK-NEXT: csel w0, w0, w8, ne
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; CHECK-NEXT: ret
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%cmp = icmp ne i32 %x, -2097152
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%sub = sub i32 -2097152, %x
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%retval.0 = select i1 %cmp, i32 %x, i32 %sub
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ret i32 %retval.0
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}
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define i32 @sgt_i32(i32 %x) {
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; CHECK-LABEL: sgt_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
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; CHECK-NEXT: cmn w0, #512, lsl #12 // =2097152
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; CHECK-NEXT: sub w8, w8, w0
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; CHECK-NEXT: csel w0, w0, w8, gt
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; CHECK-NEXT: ret
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%cmp = icmp sgt i32 %x, -2097152
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%sub = sub i32 -2097152, %x
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%retval.0 = select i1 %cmp, i32 %x, i32 %sub
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ret i32 %retval.0
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}
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define i32 @sge_i32(i32 %x) {
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; CHECK-LABEL: sge_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
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; CHECK-NEXT: mov w9, #-2097153 // =0xffdfffff
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; CHECK-NEXT: sub w8, w8, w0
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; CHECK-NEXT: cmp w0, w9
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; CHECK-NEXT: csel w0, w0, w8, gt
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; CHECK-NEXT: ret
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%cmp = icmp sge i32 %x, -2097152
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%sub = sub i32 -2097152, %x
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%retval.0 = select i1 %cmp, i32 %x, i32 %sub
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ret i32 %retval.0
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}
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define i32 @slt_i32(i32 %x) {
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; CHECK-LABEL: slt_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
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; CHECK-NEXT: cmn w0, #512, lsl #12 // =2097152
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; CHECK-NEXT: sub w8, w8, w0
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; CHECK-NEXT: csel w0, w0, w8, lt
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; CHECK-NEXT: ret
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%cmp = icmp slt i32 %x, -2097152
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%sub = sub i32 -2097152, %x
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%retval.0 = select i1 %cmp, i32 %x, i32 %sub
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ret i32 %retval.0
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}
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define i32 @sle_i32(i32 %x) {
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; CHECK-LABEL: sle_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
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; CHECK-NEXT: mov w9, #-2097151 // =0xffe00001
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; CHECK-NEXT: sub w8, w8, w0
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; CHECK-NEXT: cmp w0, w9
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; CHECK-NEXT: csel w0, w0, w8, lt
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; CHECK-NEXT: ret
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%cmp = icmp sle i32 %x, -2097152
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%sub = sub i32 -2097152, %x
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%retval.0 = select i1 %cmp, i32 %x, i32 %sub
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ret i32 %retval.0
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}
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define i32 @ugt_i32(i32 %x) {
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; CHECK-LABEL: ugt_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
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; CHECK-NEXT: cmn w0, #512, lsl #12 // =2097152
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; CHECK-NEXT: sub w8, w8, w0
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; CHECK-NEXT: csel w0, w0, w8, hi
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; CHECK-NEXT: ret
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%cmp = icmp ugt i32 %x, -2097152
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%sub = sub i32 -2097152, %x
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%retval.0 = select i1 %cmp, i32 %x, i32 %sub
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ret i32 %retval.0
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}
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define i32 @uge_i32(i32 %x) {
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; CHECK-LABEL: uge_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w9, w0, #21
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; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
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; CHECK-NEXT: sub w8, w8, w0
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; CHECK-NEXT: cmp w9, #2046
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; CHECK-NEXT: csel w0, w0, w8, hi
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; CHECK-NEXT: ret
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%cmp = icmp uge i32 %x, -2097152
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%sub = sub i32 -2097152, %x
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%retval.0 = select i1 %cmp, i32 %x, i32 %sub
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ret i32 %retval.0
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}
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define i32 @ult_i32(i32 %x) {
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; CHECK-LABEL: ult_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
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; CHECK-NEXT: cmn w0, #512, lsl #12 // =2097152
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; CHECK-NEXT: sub w8, w8, w0
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; CHECK-NEXT: csel w0, w0, w8, lo
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; CHECK-NEXT: ret
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%cmp = icmp ult i32 %x, -2097152
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%sub = sub i32 -2097152, %x
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%retval.0 = select i1 %cmp, i32 %x, i32 %sub
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ret i32 %retval.0
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}
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define i32 @ule_i32(i32 %x) {
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; CHECK-LABEL: ule_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
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; CHECK-NEXT: mov w9, #-2097151 // =0xffe00001
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; CHECK-NEXT: sub w8, w8, w0
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; CHECK-NEXT: cmp w0, w9
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; CHECK-NEXT: csel w0, w0, w8, lo
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; CHECK-NEXT: ret
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%cmp = icmp ule i32 %x, -2097152
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%sub = sub i32 -2097152, %x
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%retval.0 = select i1 %cmp, i32 %x, i32 %sub
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ret i32 %retval.0
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}
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define i64 @eq_i64(i64 %x) {
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; CHECK-LABEL: eq_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #100 // =0x64
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; CHECK-NEXT: cmp x0, #100
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; CHECK-NEXT: sub x8, x8, x0
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; CHECK-NEXT: csel x0, x0, x8, eq
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; CHECK-NEXT: ret
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%cmp = icmp eq i64 %x, 100
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%sub = sub i64 100, %x
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%retval.0 = select i1 %cmp, i64 %x, i64 %sub
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ret i64 %retval.0
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}
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define i64 @ne_i64(i64 %x) {
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; CHECK-LABEL: ne_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #100 // =0x64
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; CHECK-NEXT: cmp x0, #100
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; CHECK-NEXT: sub x8, x8, x0
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; CHECK-NEXT: csel x0, x0, x8, ne
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; CHECK-NEXT: ret
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%cmp = icmp ne i64 %x, 100
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%sub = sub i64 100, %x
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%retval.0 = select i1 %cmp, i64 %x, i64 %sub
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ret i64 %retval.0
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}
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define i64 @sgt_i64(i64 %x) {
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; CHECK-LABEL: sgt_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #100 // =0x64
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; CHECK-NEXT: cmp x0, #100
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; CHECK-NEXT: sub x8, x8, x0
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; CHECK-NEXT: csel x0, x0, x8, gt
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; CHECK-NEXT: ret
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%cmp = icmp sgt i64 %x, 100
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%sub = sub i64 100, %x
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%retval.0 = select i1 %cmp, i64 %x, i64 %sub
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ret i64 %retval.0
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}
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define i64 @sge_i64(i64 %x) {
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; CHECK-LABEL: sge_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #100 // =0x64
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; CHECK-NEXT: cmp x0, #99
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; CHECK-NEXT: sub x8, x8, x0
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; CHECK-NEXT: csel x0, x0, x8, gt
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; CHECK-NEXT: ret
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%cmp = icmp sge i64 %x, 100
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%sub = sub i64 100, %x
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%retval.0 = select i1 %cmp, i64 %x, i64 %sub
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ret i64 %retval.0
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}
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define i64 @slt_i64(i64 %x) {
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; CHECK-LABEL: slt_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #100 // =0x64
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; CHECK-NEXT: cmp x0, #100
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; CHECK-NEXT: sub x8, x8, x0
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; CHECK-NEXT: csel x0, x0, x8, lt
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; CHECK-NEXT: ret
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%cmp = icmp slt i64 %x, 100
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%sub = sub i64 100, %x
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%retval.0 = select i1 %cmp, i64 %x, i64 %sub
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ret i64 %retval.0
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}
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define i64 @sle_i64(i64 %x) {
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; CHECK-LABEL: sle_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #100 // =0x64
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; CHECK-NEXT: cmp x0, #101
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; CHECK-NEXT: sub x8, x8, x0
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; CHECK-NEXT: csel x0, x0, x8, lt
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; CHECK-NEXT: ret
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%cmp = icmp sle i64 %x, 100
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%sub = sub i64 100, %x
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%retval.0 = select i1 %cmp, i64 %x, i64 %sub
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ret i64 %retval.0
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}
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define i64 @ugt_i64(i64 %x) {
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; CHECK-LABEL: ugt_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #100 // =0x64
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; CHECK-NEXT: cmp x0, #100
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; CHECK-NEXT: sub x8, x8, x0
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; CHECK-NEXT: csel x0, x0, x8, hi
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; CHECK-NEXT: ret
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%cmp = icmp ugt i64 %x, 100
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%sub = sub i64 100, %x
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%retval.0 = select i1 %cmp, i64 %x, i64 %sub
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ret i64 %retval.0
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}
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define i64 @uge_i64(i64 %x) {
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; CHECK-LABEL: uge_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #100 // =0x64
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; CHECK-NEXT: cmp x0, #99
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; CHECK-NEXT: sub x8, x8, x0
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; CHECK-NEXT: csel x0, x0, x8, hi
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; CHECK-NEXT: ret
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%cmp = icmp uge i64 %x, 100
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%sub = sub i64 100, %x
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%retval.0 = select i1 %cmp, i64 %x, i64 %sub
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ret i64 %retval.0
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}
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define i64 @ult_i64(i64 %x) {
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; CHECK-LABEL: ult_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #100 // =0x64
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; CHECK-NEXT: cmp x0, #100
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; CHECK-NEXT: sub x8, x8, x0
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; CHECK-NEXT: csel x0, x0, x8, lo
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; CHECK-NEXT: ret
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%cmp = icmp ult i64 %x, 100
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%sub = sub i64 100, %x
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%retval.0 = select i1 %cmp, i64 %x, i64 %sub
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ret i64 %retval.0
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}
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define i64 @ule_i64(i64 %x) {
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; CHECK-LABEL: ule_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #100 // =0x64
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; CHECK-NEXT: cmp x0, #101
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; CHECK-NEXT: sub x8, x8, x0
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; CHECK-NEXT: csel x0, x0, x8, lo
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; CHECK-NEXT: ret
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%cmp = icmp ule i64 %x, 100
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%sub = sub i64 100, %x
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%retval.0 = select i1 %cmp, i64 %x, i64 %sub
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ret i64 %retval.0
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}
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define i64 @both(i64 %x) {
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; CHECK-LABEL: both:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #100 // =0x64
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; CHECK-NEXT: sub x9, x0, #100
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; CHECK-NEXT: cmp x0, #101
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; CHECK-NEXT: sub x8, x8, x0
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; CHECK-NEXT: csel x0, x8, x9, lo
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; CHECK-NEXT: ret
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%cmp = icmp ule i64 %x, 100
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%sub1 = sub i64 100, %x
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%sub2 = sub i64 %x, 100
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%retval.0 = select i1 %cmp, i64 %sub1, i64 %sub2
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ret i64 %retval.0
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}
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define i32 @qabs(i32 %0) {
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; CHECK-LABEL: qabs:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000
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; CHECK-NEXT: cmp w0, w8
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; CHECK-NEXT: mov w8, #2147483647 // =0x7fffffff
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; CHECK-NEXT: csneg w8, w8, w0, eq
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: csel w0, w0, w8, gt
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; CHECK-NEXT: ret
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%cmp1 = icmp sgt i32 %0, 0
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%cmp2 = icmp eq i32 %0, -2147483648
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%sub = sub nsw i32 0, %0
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%cond = select i1 %cmp2, i32 2147483647, i32 %sub
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%cond6 = select i1 %cmp1, i32 %0, i32 %cond
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ret i32 %cond6
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}

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