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Simplify EmitZaInstr with StartIdx
1 parent 5d1ef11 commit 2d128fb

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2 files changed

+10
-13
lines changed

2 files changed

+10
-13
lines changed

clang/test/CodeGen/aarch64-sme2p1-intrinsics/acle_sme2p1_movaz.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
2-
//RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
3-
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
2+
//RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s
3+
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
44
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
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66
#include <arm_sme.h>

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2958,17 +2958,15 @@ AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
29582958
bool HasZPROut = HasTile && MI.getOperand(0).isReg();
29592959
if (HasZPROut) {
29602960
MIB.add(MI.getOperand(0)); // Output ZPR
2961-
MIB.addReg(BaseReg + MI.getOperand(1).getImm(),
2962-
RegState::Define); // Output ZA Tile
2963-
MIB.addReg(BaseReg + MI.getOperand(1).getImm()); // Input Za Tile
2964-
StartIdx = 2;
2961+
++StartIdx;
2962+
}
2963+
if (HasTile) {
2964+
MIB.addReg(BaseReg + MI.getOperand(StartIdx).getImm(),
2965+
RegState::Define); // Output ZA Tile
2966+
MIB.addReg(BaseReg + MI.getOperand(StartIdx).getImm()); // Input Za Tile
2967+
StartIdx++;
29652968
} else {
2966-
if (HasTile) {
2967-
MIB.addReg(BaseReg + MI.getOperand(0).getImm(), RegState::Define);
2968-
MIB.addReg(BaseReg + MI.getOperand(0).getImm());
2969-
StartIdx = 1;
2970-
} else
2971-
MIB.addReg(BaseReg, RegState::Define).addReg(BaseReg);
2969+
MIB.addReg(BaseReg, RegState::Define).addReg(BaseReg);
29722970
}
29732971
for (unsigned I = StartIdx; I < MI.getNumOperands(); ++I)
29742972
MIB.add(MI.getOperand(I));
@@ -3009,7 +3007,6 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
30093007
return EmitZAInstr(SMEOrigInstr, AArch64::ZAB0, MI, BB);
30103008
case (AArch64::SMEMatrixTileH):
30113009
return EmitZAInstr(SMEOrigInstr, AArch64::ZAH0, MI, BB);
3012-
///*HasTile*/ true, /*HasZPROut*/ false);
30133010
case (AArch64::SMEMatrixTileS):
30143011
return EmitZAInstr(SMEOrigInstr, AArch64::ZAS0, MI, BB);
30153012
case (AArch64::SMEMatrixTileD):

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