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jayfoadjayfoad
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[AMDGPU] Reduce duplication in SOP instruction definitions. NFCI. (#80413)
Use !tolower instead of repeating the name when defining a renamed Real instruction.
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‎llvm/lib/Target/AMDGPU/SOPInstructions.td

Lines changed: 60 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -1970,13 +1970,15 @@ multiclass SOP1_Real_gfx11<bits<8> op> {
19701970
Select_gfx11<!cast<SOP1_Pseudo>(NAME).Mnemonic>;
19711971
}
19721972

1973-
multiclass SOP1_Real_Renamed_gfx12<bits<8> op, SOP1_Pseudo backing_pseudo, string real_name> {
1973+
multiclass SOP1_Real_Renamed_gfx12<bits<8> op, SOP1_Pseudo backing_pseudo> {
1974+
defvar real_name = !tolower(NAME);
19741975
def _gfx12 : SOP1_Real<op, backing_pseudo, real_name>,
19751976
Select_gfx12<backing_pseudo.Mnemonic>,
19761977
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX12Plus]>;
19771978
}
19781979

1979-
multiclass SOP1_Real_Renamed_gfx11<bits<8> op, SOP1_Pseudo backing_pseudo, string real_name> {
1980+
multiclass SOP1_Real_Renamed_gfx11<bits<8> op, SOP1_Pseudo backing_pseudo> {
1981+
defvar real_name = !tolower(NAME);
19801982
def _gfx11 : SOP1_Real<op, backing_pseudo, real_name>,
19811983
Select_gfx11<backing_pseudo.Mnemonic>,
19821984
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX11Only]>;
@@ -1985,22 +1987,22 @@ multiclass SOP1_Real_Renamed_gfx11<bits<8> op, SOP1_Pseudo backing_pseudo, strin
19851987
multiclass SOP1_Real_gfx11_gfx12<bits<8> op> :
19861988
SOP1_Real_gfx11<op>, SOP1_Real_gfx12<op>;
19871989

1988-
multiclass SOP1_Real_Renamed_gfx11_gfx12<bits<8> op, SOP1_Pseudo backing_pseudo, string real_name> :
1989-
SOP1_Real_Renamed_gfx11<op, backing_pseudo, real_name>,
1990-
SOP1_Real_Renamed_gfx12<op, backing_pseudo, real_name>;
1990+
multiclass SOP1_Real_Renamed_gfx11_gfx12<bits<8> op, SOP1_Pseudo backing_pseudo> :
1991+
SOP1_Real_Renamed_gfx11<op, backing_pseudo>,
1992+
SOP1_Real_Renamed_gfx12<op, backing_pseudo>;
19911993

19921994
defm S_MOV_B32 : SOP1_Real_gfx11_gfx12<0x000>;
19931995
defm S_MOV_B64 : SOP1_Real_gfx11_gfx12<0x001>;
19941996
defm S_CMOV_B32 : SOP1_Real_gfx11_gfx12<0x002>;
19951997
defm S_CMOV_B64 : SOP1_Real_gfx11_gfx12<0x003>;
19961998
defm S_BREV_B32 : SOP1_Real_gfx11_gfx12<0x004>;
19971999
defm S_BREV_B64 : SOP1_Real_gfx11_gfx12<0x005>;
1998-
defm S_CTZ_I32_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x008, S_FF1_I32_B32, "s_ctz_i32_b32">;
1999-
defm S_CTZ_I32_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x009, S_FF1_I32_B64, "s_ctz_i32_b64">;
2000-
defm S_CLZ_I32_U32 : SOP1_Real_Renamed_gfx11_gfx12<0x00a, S_FLBIT_I32_B32, "s_clz_i32_u32">;
2001-
defm S_CLZ_I32_U64 : SOP1_Real_Renamed_gfx11_gfx12<0x00b, S_FLBIT_I32_B64, "s_clz_i32_u64">;
2002-
defm S_CLS_I32 : SOP1_Real_Renamed_gfx11_gfx12<0x00c, S_FLBIT_I32, "s_cls_i32">;
2003-
defm S_CLS_I32_I64 : SOP1_Real_Renamed_gfx11_gfx12<0x00d, S_FLBIT_I32_I64, "s_cls_i32_i64">;
2000+
defm S_CTZ_I32_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x008, S_FF1_I32_B32>;
2001+
defm S_CTZ_I32_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x009, S_FF1_I32_B64>;
2002+
defm S_CLZ_I32_U32 : SOP1_Real_Renamed_gfx11_gfx12<0x00a, S_FLBIT_I32_B32>;
2003+
defm S_CLZ_I32_U64 : SOP1_Real_Renamed_gfx11_gfx12<0x00b, S_FLBIT_I32_B64>;
2004+
defm S_CLS_I32 : SOP1_Real_Renamed_gfx11_gfx12<0x00c, S_FLBIT_I32>;
2005+
defm S_CLS_I32_I64 : SOP1_Real_Renamed_gfx11_gfx12<0x00d, S_FLBIT_I32_I64>;
20042006
defm S_SEXT_I32_I8 : SOP1_Real_gfx11_gfx12<0x00e>;
20052007
defm S_SEXT_I32_I16 : SOP1_Real_gfx11_gfx12<0x00f>;
20062008
defm S_BITSET0_B32 : SOP1_Real_gfx11_gfx12<0x010>;
@@ -2031,18 +2033,18 @@ defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x028>;
20312033
defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x029>;
20322034
defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x02a>;
20332035
/*defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x02b>; //same as older arch, handled there*/
2034-
defm S_AND_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x02c, S_ANDN1_SAVEEXEC_B32, "s_and_not0_saveexec_b32">;
2035-
defm S_AND_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x02d, S_ANDN1_SAVEEXEC_B64, "s_and_not0_saveexec_b64">;
2036-
defm S_OR_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x02e, S_ORN1_SAVEEXEC_B32, "s_or_not0_saveexec_b32">;
2037-
defm S_OR_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x02f, S_ORN1_SAVEEXEC_B64, "s_or_not0_saveexec_b64">;
2038-
defm S_AND_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x030, S_ANDN2_SAVEEXEC_B32, "s_and_not1_saveexec_b32">;
2039-
defm S_AND_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x031, S_ANDN2_SAVEEXEC_B64, "s_and_not1_saveexec_b64">;
2040-
defm S_OR_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x032, S_ORN2_SAVEEXEC_B32, "s_or_not1_saveexec_b32">;
2041-
defm S_OR_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x033, S_ORN2_SAVEEXEC_B64, "s_or_not1_saveexec_b64">;
2042-
defm S_AND_NOT0_WREXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x034, S_ANDN1_WREXEC_B32, "s_and_not0_wrexec_b32">;
2043-
defm S_AND_NOT0_WREXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x035, S_ANDN1_WREXEC_B64, "s_and_not0_wrexec_b64">;
2044-
defm S_AND_NOT1_WREXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x036, S_ANDN2_WREXEC_B32, "s_and_not1_wrexec_b32">;
2045-
defm S_AND_NOT1_WREXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x037, S_ANDN2_WREXEC_B64, "s_and_not1_wrexec_b64">;
2036+
defm S_AND_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x02c, S_ANDN1_SAVEEXEC_B32>;
2037+
defm S_AND_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x02d, S_ANDN1_SAVEEXEC_B64>;
2038+
defm S_OR_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x02e, S_ORN1_SAVEEXEC_B32>;
2039+
defm S_OR_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x02f, S_ORN1_SAVEEXEC_B64>;
2040+
defm S_AND_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x030, S_ANDN2_SAVEEXEC_B32>;
2041+
defm S_AND_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x031, S_ANDN2_SAVEEXEC_B64>;
2042+
defm S_OR_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x032, S_ORN2_SAVEEXEC_B32>;
2043+
defm S_OR_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x033, S_ORN2_SAVEEXEC_B64>;
2044+
defm S_AND_NOT0_WREXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x034, S_ANDN1_WREXEC_B32>;
2045+
defm S_AND_NOT0_WREXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x035, S_ANDN1_WREXEC_B64>;
2046+
defm S_AND_NOT1_WREXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x036, S_ANDN2_WREXEC_B32>;
2047+
defm S_AND_NOT1_WREXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x037, S_ANDN2_WREXEC_B64>;
20462048
defm S_MOVRELS_B32 : SOP1_Real_gfx11_gfx12<0x040>;
20472049
defm S_MOVRELS_B64 : SOP1_Real_gfx11_gfx12<0x041>;
20482050
defm S_MOVRELD_B32 : SOP1_Real_gfx11_gfx12<0x042>;
@@ -2196,27 +2198,28 @@ multiclass SOP2_Real_gfx12<bits<7> op> {
21962198
Select_gfx12<!cast<SOP2_Pseudo>(NAME).Mnemonic>;
21972199
}
21982200

2199-
multiclass SOP2_Real_Renamed_gfx12<bits<7> op, SOP2_Pseudo backing_pseudo, string real_name> {
2201+
multiclass SOP2_Real_Renamed_gfx12<bits<7> op, SOP2_Pseudo backing_pseudo> {
2202+
defvar real_name = !tolower(NAME);
22002203
def _gfx12 : SOP2_Real32<op, backing_pseudo, real_name>,
22012204
Select_gfx12<backing_pseudo.Mnemonic>,
22022205
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX12Plus]>;
22032206
}
22042207

2205-
defm S_MIN_NUM_F32 : SOP2_Real_Renamed_gfx12<0x042, S_MIN_F32, "s_min_num_f32">;
2206-
defm S_MAX_NUM_F32 : SOP2_Real_Renamed_gfx12<0x043, S_MAX_F32, "s_max_num_f32">;
2207-
defm S_MIN_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04b, S_MIN_F16, "s_min_num_f16">;
2208-
defm S_MAX_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04c, S_MAX_F16, "s_max_num_f16">;
2208+
defm S_MIN_NUM_F32 : SOP2_Real_Renamed_gfx12<0x042, S_MIN_F32>;
2209+
defm S_MAX_NUM_F32 : SOP2_Real_Renamed_gfx12<0x043, S_MAX_F32>;
2210+
defm S_MIN_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04b, S_MIN_F16>;
2211+
defm S_MAX_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04c, S_MAX_F16>;
22092212
defm S_MINIMUM_F32 : SOP2_Real_gfx12<0x04f>;
22102213
defm S_MAXIMUM_F32 : SOP2_Real_gfx12<0x050>;
22112214
defm S_MINIMUM_F16 : SOP2_Real_gfx12<0x051>;
22122215
defm S_MAXIMUM_F16 : SOP2_Real_gfx12<0x052>;
22132216

2214-
defm S_ADD_CO_U32 : SOP2_Real_Renamed_gfx12<0x000, S_ADD_U32, "s_add_co_u32">;
2215-
defm S_SUB_CO_U32 : SOP2_Real_Renamed_gfx12<0x001, S_SUB_U32, "s_sub_co_u32">;
2216-
defm S_ADD_CO_I32 : SOP2_Real_Renamed_gfx12<0x002, S_ADD_I32, "s_add_co_i32">;
2217-
defm S_SUB_CO_I32 : SOP2_Real_Renamed_gfx12<0x003, S_SUB_I32, "s_sub_co_i32">;
2218-
defm S_ADD_CO_CI_U32 : SOP2_Real_Renamed_gfx12<0x004, S_ADDC_U32, "s_add_co_ci_u32">;
2219-
defm S_SUB_CO_CI_U32 : SOP2_Real_Renamed_gfx12<0x005, S_SUBB_U32, "s_sub_co_ci_u32">;
2217+
defm S_ADD_CO_U32 : SOP2_Real_Renamed_gfx12<0x000, S_ADD_U32>;
2218+
defm S_SUB_CO_U32 : SOP2_Real_Renamed_gfx12<0x001, S_SUB_U32>;
2219+
defm S_ADD_CO_I32 : SOP2_Real_Renamed_gfx12<0x002, S_ADD_I32>;
2220+
defm S_SUB_CO_I32 : SOP2_Real_Renamed_gfx12<0x003, S_SUB_I32>;
2221+
defm S_ADD_CO_CI_U32 : SOP2_Real_Renamed_gfx12<0x004, S_ADDC_U32>;
2222+
defm S_SUB_CO_CI_U32 : SOP2_Real_Renamed_gfx12<0x005, S_SUBB_U32>;
22202223

22212224
//===----------------------------------------------------------------------===//
22222225
// SOP2 - GFX11, GFX12.
@@ -2227,7 +2230,8 @@ multiclass SOP2_Real_gfx11<bits<7> op> {
22272230
Select_gfx11<!cast<SOP2_Pseudo>(NAME).Mnemonic>;
22282231
}
22292232

2230-
multiclass SOP2_Real_Renamed_gfx11<bits<7> op, SOP2_Pseudo backing_pseudo, string real_name> {
2233+
multiclass SOP2_Real_Renamed_gfx11<bits<7> op, SOP2_Pseudo backing_pseudo> {
2234+
defvar real_name = !tolower(NAME);
22312235
def _gfx11 : SOP2_Real32<op, backing_pseudo, real_name>,
22322236
Select_gfx11<backing_pseudo.Mnemonic>,
22332237
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX11Only]>;
@@ -2236,9 +2240,9 @@ multiclass SOP2_Real_Renamed_gfx11<bits<7> op, SOP2_Pseudo backing_pseudo, strin
22362240
multiclass SOP2_Real_gfx11_gfx12<bits<7> op> :
22372241
SOP2_Real_gfx11<op>, SOP2_Real_gfx12<op>;
22382242

2239-
multiclass SOP2_Real_Renamed_gfx11_gfx12<bits<8> op, SOP2_Pseudo backing_pseudo, string real_name> :
2240-
SOP2_Real_Renamed_gfx11<op, backing_pseudo, real_name>,
2241-
SOP2_Real_Renamed_gfx12<op, backing_pseudo, real_name>;
2243+
multiclass SOP2_Real_Renamed_gfx11_gfx12<bits<8> op, SOP2_Pseudo backing_pseudo> :
2244+
SOP2_Real_Renamed_gfx11<op, backing_pseudo>,
2245+
SOP2_Real_Renamed_gfx12<op, backing_pseudo>;
22422246

22432247
defm S_ABSDIFF_I32 : SOP2_Real_gfx11_gfx12<0x006>;
22442248
defm S_LSHL_B32 : SOP2_Real_gfx11_gfx12<0x008>;
@@ -2267,10 +2271,10 @@ defm S_NOR_B32 : SOP2_Real_gfx11_gfx12<0x01e>;
22672271
defm S_NOR_B64 : SOP2_Real_gfx11_gfx12<0x01f>;
22682272
defm S_XNOR_B32 : SOP2_Real_gfx11_gfx12<0x020>;
22692273
defm S_XNOR_B64 : SOP2_Real_gfx11_gfx12<0x021>;
2270-
defm S_AND_NOT1_B32 : SOP2_Real_Renamed_gfx11_gfx12<0x022, S_ANDN2_B32, "s_and_not1_b32">;
2271-
defm S_AND_NOT1_B64 : SOP2_Real_Renamed_gfx11_gfx12<0x023, S_ANDN2_B64, "s_and_not1_b64">;
2272-
defm S_OR_NOT1_B32 : SOP2_Real_Renamed_gfx11_gfx12<0x024, S_ORN2_B32, "s_or_not1_b32">;
2273-
defm S_OR_NOT1_B64 : SOP2_Real_Renamed_gfx11_gfx12<0x025, S_ORN2_B64, "s_or_not1_b64">;
2274+
defm S_AND_NOT1_B32 : SOP2_Real_Renamed_gfx11_gfx12<0x022, S_ANDN2_B32>;
2275+
defm S_AND_NOT1_B64 : SOP2_Real_Renamed_gfx11_gfx12<0x023, S_ANDN2_B64>;
2276+
defm S_OR_NOT1_B32 : SOP2_Real_Renamed_gfx11_gfx12<0x024, S_ORN2_B32>;
2277+
defm S_OR_NOT1_B64 : SOP2_Real_Renamed_gfx11_gfx12<0x025, S_ORN2_B64>;
22742278
defm S_BFE_U32 : SOP2_Real_gfx11_gfx12<0x026>;
22752279
defm S_BFE_I32 : SOP2_Real_gfx11_gfx12<0x027>;
22762280
defm S_BFE_U64 : SOP2_Real_gfx11_gfx12<0x028>;
@@ -2283,8 +2287,8 @@ defm S_MUL_HI_I32 : SOP2_Real_gfx11_gfx12<0x02e>;
22832287
defm S_CSELECT_B32 : SOP2_Real_gfx11_gfx12<0x030>;
22842288
defm S_CSELECT_B64 : SOP2_Real_gfx11_gfx12<0x031>;
22852289
defm S_PACK_HL_B32_B16 : SOP2_Real_gfx11_gfx12<0x035>;
2286-
defm S_ADD_NC_U64 : SOP2_Real_Renamed_gfx12<0x053, S_ADD_U64, "s_add_nc_u64">;
2287-
defm S_SUB_NC_U64 : SOP2_Real_Renamed_gfx12<0x054, S_SUB_U64, "s_sub_nc_u64">;
2290+
defm S_ADD_NC_U64 : SOP2_Real_Renamed_gfx12<0x053, S_ADD_U64>;
2291+
defm S_SUB_NC_U64 : SOP2_Real_Renamed_gfx12<0x054, S_SUB_U64>;
22882292
defm S_MUL_U64 : SOP2_Real_gfx12<0x055>;
22892293

22902294
//===----------------------------------------------------------------------===//
@@ -2421,7 +2425,8 @@ multiclass SOPK_Real32_gfx12<bits<5> op> {
24212425
Select_gfx12<!cast<SOPK_Pseudo>(NAME).Mnemonic>;
24222426
}
24232427

2424-
multiclass SOPK_Real32_Renamed_gfx12<bits<5> op, SOPK_Pseudo backing_pseudo, string real_name> {
2428+
multiclass SOPK_Real32_Renamed_gfx12<bits<5> op, SOPK_Pseudo backing_pseudo> {
2429+
defvar real_name = !tolower(NAME);
24252430
def _gfx12 : SOPK_Real32<op, backing_pseudo, real_name>,
24262431
Select_gfx12<backing_pseudo.Mnemonic>,
24272432
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX12Plus]>;
@@ -2448,7 +2453,7 @@ multiclass SOPK_Real32_gfx11_gfx12<bits<5> op> :
24482453
multiclass SOPK_Real64_gfx11_gfx12<bits<5> op> :
24492454
SOPK_Real64_gfx11<op>, SOPK_Real64_gfx12<op>;
24502455

2451-
defm S_ADDK_CO_I32 : SOPK_Real32_Renamed_gfx12<0x00f, S_ADDK_I32, "s_addk_co_i32">;
2456+
defm S_ADDK_CO_I32 : SOPK_Real32_Renamed_gfx12<0x00f, S_ADDK_I32>;
24522457
defm S_GETREG_B32 : SOPK_Real32_gfx11_gfx12<0x011>;
24532458
defm S_SETREG_B32 : SOPK_Real32_gfx11_gfx12<0x012>;
24542459
defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx11_gfx12<0x013>;
@@ -2551,13 +2556,14 @@ multiclass SOPP_Real_32_gfx12<bits<7> op> {
25512556
SOPPRelaxTable<0, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx12">;
25522557
}
25532558

2554-
multiclass SOPP_Real_32_Renamed_gfx12<bits<7> op, SOPP_Pseudo backing_pseudo, string real_name> {
2559+
multiclass SOPP_Real_32_Renamed_gfx12<bits<7> op, SOPP_Pseudo backing_pseudo> {
2560+
defvar real_name = !tolower(NAME);
25552561
def _gfx12 : SOPP_Real_32<op, backing_pseudo, real_name>,
25562562
Select_gfx12<backing_pseudo.Mnemonic>,
25572563
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX12Plus]>;
25582564
}
25592565

2560-
defm S_WAIT_ALU : SOPP_Real_32_Renamed_gfx12<0x008, S_WAITCNT_DEPCTR, "s_wait_alu">;
2566+
defm S_WAIT_ALU : SOPP_Real_32_Renamed_gfx12<0x008, S_WAITCNT_DEPCTR>;
25612567
defm S_BARRIER_WAIT : SOPP_Real_32_gfx12<0x014>;
25622568
defm S_BARRIER_LEAVE : SOPP_Real_32_gfx12<0x015>;
25632569
defm S_WAIT_LOADCNT : SOPP_Real_32_gfx12<0x040>;
@@ -2593,7 +2599,8 @@ multiclass SOPP_Real_64_gfx11<bits<7> op> {
25932599
SOPPRelaxTable<1, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx11">;
25942600
}
25952601

2596-
multiclass SOPP_Real_32_Renamed_gfx11<bits<7> op, SOPP_Pseudo backing_pseudo, string real_name> {
2602+
multiclass SOPP_Real_32_Renamed_gfx11<bits<7> op, SOPP_Pseudo backing_pseudo> {
2603+
defvar real_name = !tolower(NAME);
25972604
def _gfx11 : SOPP_Real_32<op, backing_pseudo, real_name>,
25982605
Select_gfx11<backing_pseudo.Mnemonic>,
25992606
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX11Only]>;
@@ -2605,9 +2612,9 @@ multiclass SOPP_Real_32_gfx11_gfx12<bits<7> op> :
26052612
multiclass SOPP_Real_64_gfx11_gfx12<bits<7> op> :
26062613
SOPP_Real_64_gfx11<op>, SOPP_Real_64_gfx12<op>;
26072614

2608-
multiclass SOPP_Real_32_Renamed_gfx11_gfx12<bits<7> op, SOPP_Pseudo backing_pseudo, string real_name> :
2609-
SOPP_Real_32_Renamed_gfx11<op, backing_pseudo, real_name>,
2610-
SOPP_Real_32_Renamed_gfx12<op, backing_pseudo, real_name>;
2615+
multiclass SOPP_Real_32_Renamed_gfx11_gfx12<bits<7> op, SOPP_Pseudo backing_pseudo> :
2616+
SOPP_Real_32_Renamed_gfx11<op, backing_pseudo>,
2617+
SOPP_Real_32_Renamed_gfx12<op, backing_pseudo>;
26112618

26122619
multiclass SOPP_Real_With_Relaxation_gfx12<bits<7> op> {
26132620
defm "" : SOPP_Real_32_gfx12<op>;
@@ -2625,7 +2632,7 @@ multiclass SOPP_Real_With_Relaxation_gfx11_gfx12<bits<7>op> :
26252632
defm S_SETKILL : SOPP_Real_32_gfx11_gfx12<0x001>;
26262633
defm S_SETHALT : SOPP_Real_32_gfx11_gfx12<0x002>;
26272634
defm S_SLEEP : SOPP_Real_32_gfx11_gfx12<0x003>;
2628-
defm S_SET_INST_PREFETCH_DISTANCE : SOPP_Real_32_Renamed_gfx11<0x004, S_INST_PREFETCH, "s_set_inst_prefetch_distance">;
2635+
defm S_SET_INST_PREFETCH_DISTANCE : SOPP_Real_32_Renamed_gfx11<0x004, S_INST_PREFETCH>;
26292636
defm S_CLAUSE : SOPP_Real_32_gfx11_gfx12<0x005>;
26302637
defm S_DELAY_ALU : SOPP_Real_32_gfx11_gfx12<0x007>;
26312638
defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx11<0x008>;

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