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[SelectionDAG] Add and use SDNode::getAsAPIntVal() helper (#77455)
This is the logical equivalent for #76710 for APInt and uses the same naming scheme. Converted existing users through: `git grep -l "cast<ConstantSDNode>\(.*\).*getAPIntValueValue" | xargs sed -E -i 's/cast<ConstantSDNode>\((.*)\)->getAPIntValue/\1->getAsAPIntVal/'`
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12 files changed

+36
-31
lines changed

12 files changed

+36
-31
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -935,6 +935,9 @@ END_TWO_BYTE_PACK()
935935
/// Helper method returns the APInt of a ConstantSDNode operand.
936936
inline const APInt &getConstantOperandAPInt(unsigned Num) const;
937937

938+
/// Helper method returns the APInt value of a ConstantSDNode.
939+
inline const APInt &getAsAPIntVal() const;
940+
938941
const SDValue &getOperand(unsigned Num) const {
939942
assert(Num < NumOperands && "Invalid child # of SDNode!");
940943
return OperandList[Num];
@@ -1656,6 +1659,10 @@ const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
16561659
return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
16571660
}
16581661

1662+
const APInt &SDNode::getAsAPIntVal() const {
1663+
return cast<ConstantSDNode>(this)->getAPIntValue();
1664+
}
1665+
16591666
class ConstantFPSDNode : public SDNode {
16601667
friend class SelectionDAG;
16611668

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -4380,7 +4380,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
43804380
} else {
43814381
N1IsConst = isa<ConstantSDNode>(N1);
43824382
if (N1IsConst) {
4383-
ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
4383+
ConstValue1 = N1->getAsAPIntVal();
43844384
N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
43854385
}
43864386
}
@@ -12087,8 +12087,8 @@ SDValue DAGCombiner::foldVSelectOfConstants(SDNode *N) {
1208712087
if (N1Elt.getValueType() != N2Elt.getValueType())
1208812088
continue;
1208912089

12090-
const APInt &C1 = cast<ConstantSDNode>(N1Elt)->getAPIntValue();
12091-
const APInt &C2 = cast<ConstantSDNode>(N2Elt)->getAPIntValue();
12090+
const APInt &C1 = N1Elt->getAsAPIntVal();
12091+
const APInt &C2 = N2Elt->getAsAPIntVal();
1209212092
if (C1 != C2 + 1)
1209312093
AllAddOne = false;
1209412094
if (C1 != C2 - 1)
@@ -12764,7 +12764,7 @@ static SDValue tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
1276412764
SDLoc DL(Op);
1276512765
// Get the constant value and if needed trunc it to the size of the type.
1276612766
// Nodes like build_vector might have constants wider than the scalar type.
12767-
APInt C = cast<ConstantSDNode>(Op)->getAPIntValue().zextOrTrunc(EVTBits);
12767+
APInt C = Op->getAsAPIntVal().zextOrTrunc(EVTBits);
1276812768
if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
1276912769
Elts.push_back(DAG.getConstant(C.sext(VTBits), DL, SVT));
1277012770
else
@@ -17942,10 +17942,10 @@ SDValue DAGCombiner::rebuildSetCC(SDValue N) {
1794217942
SDValue AndOp1 = Op0.getOperand(1);
1794317943

1794417944
if (AndOp1.getOpcode() == ISD::Constant) {
17945-
const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
17945+
const APInt &AndConst = AndOp1->getAsAPIntVal();
1794617946

1794717947
if (AndConst.isPowerOf2() &&
17948-
cast<ConstantSDNode>(Op1)->getAPIntValue() == AndConst.logBase2()) {
17948+
Op1->getAsAPIntVal() == AndConst.logBase2()) {
1794917949
SDLoc DL(N);
1795017950
return DAG.getSetCC(DL, getSetCCResultType(Op0.getValueType()),
1795117951
Op0, DAG.getConstant(0, DL, Op0.getValueType()),
@@ -18266,7 +18266,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
1826618266

1826718267
auto *CN = cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
1826818268
const APInt &Offset0 = CN->getAPIntValue();
18269-
const APInt &Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
18269+
const APInt &Offset1 = Offset->getAsAPIntVal();
1827018270
int X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
1827118271
int Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
1827218272
int X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
@@ -19573,7 +19573,7 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
1957319573
// Find the type to narrow it the load / op / store to.
1957419574
SDValue N1 = Value.getOperand(1);
1957519575
unsigned BitWidth = N1.getValueSizeInBits();
19576-
APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
19576+
APInt Imm = N1->getAsAPIntVal();
1957719577
if (Opc == ISD::AND)
1957819578
Imm ^= APInt::getAllOnes(BitWidth);
1957919579
if (Imm == 0 || Imm.isAllOnes())
@@ -26543,7 +26543,7 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
2654326543

2654426544
APInt Bits;
2654526545
if (isa<ConstantSDNode>(Elt))
26546-
Bits = cast<ConstantSDNode>(Elt)->getAPIntValue();
26546+
Bits = Elt->getAsAPIntVal();
2654726547
else if (isa<ConstantFPSDNode>(Elt))
2654826548
Bits = cast<ConstantFPSDNode>(Elt)->getValueAPF().bitcastToAPInt();
2654926549
else

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1854,7 +1854,7 @@ void DAGTypeLegalizer::SplitVecRes_STEP_VECTOR(SDNode *N, SDValue &Lo,
18541854

18551855
// Hi = Lo + (EltCnt * Step)
18561856
EVT EltVT = Step.getValueType();
1857-
APInt StepVal = cast<ConstantSDNode>(Step)->getAPIntValue();
1857+
APInt StepVal = Step->getAsAPIntVal();
18581858
SDValue StartOfHi =
18591859
DAG.getVScale(dl, EltVT, StepVal * LoVT.getVectorMinNumElements());
18601860
StartOfHi = DAG.getSExtOrTrunc(StartOfHi, dl, HiVT.getVectorElementType());

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -327,7 +327,7 @@ bool ISD::isVectorShrinkable(const SDNode *N, unsigned NewEltSize,
327327
if (!isa<ConstantSDNode>(Op))
328328
return false;
329329

330-
APInt C = cast<ConstantSDNode>(Op)->getAPIntValue().trunc(EltSize);
330+
APInt C = Op->getAsAPIntVal().trunc(EltSize);
331331
if (Signed && C.trunc(NewEltSize).sext(EltSize) != C)
332332
return false;
333333
if (!Signed && C.trunc(NewEltSize).zext(EltSize) != C)
@@ -7200,7 +7200,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
72007200
(N2VT.getVectorMinNumElements() + N3->getAsZExtVal()) <=
72017201
VT.getVectorMinNumElements()) &&
72027202
"Insert subvector overflow!");
7203-
assert(cast<ConstantSDNode>(N3)->getAPIntValue().getBitWidth() ==
7203+
assert(N3->getAsAPIntVal().getBitWidth() ==
72047204
TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&
72057205
"Constant index for INSERT_SUBVECTOR has an invalid size");
72067206

@@ -9304,7 +9304,7 @@ SDValue SelectionDAG::getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl,
93049304
N->getValueType(0).getVectorElementCount()) &&
93059305
"Vector width mismatch between index and data");
93069306
assert(isa<ConstantSDNode>(N->getScale()) &&
9307-
cast<ConstantSDNode>(N->getScale())->getAPIntValue().isPowerOf2() &&
9307+
N->getScale()->getAsAPIntVal().isPowerOf2() &&
93089308
"Scale should be a constant power of 2");
93099309

93109310
CSEMap.InsertNode(N, IP);
@@ -9348,7 +9348,7 @@ SDValue SelectionDAG::getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl,
93489348
N->getValue().getValueType().getVectorElementCount()) &&
93499349
"Vector width mismatch between index and data");
93509350
assert(isa<ConstantSDNode>(N->getScale()) &&
9351-
cast<ConstantSDNode>(N->getScale())->getAPIntValue().isPowerOf2() &&
9351+
N->getScale()->getAsAPIntVal().isPowerOf2() &&
93529352
"Scale should be a constant power of 2");
93539353

93549354
CSEMap.InsertNode(N, IP);
@@ -9490,7 +9490,7 @@ SDValue SelectionDAG::getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl,
94909490
N->getValueType(0).getVectorElementCount()) &&
94919491
"Vector width mismatch between index and data");
94929492
assert(isa<ConstantSDNode>(N->getScale()) &&
9493-
cast<ConstantSDNode>(N->getScale())->getAPIntValue().isPowerOf2() &&
9493+
N->getScale()->getAsAPIntVal().isPowerOf2() &&
94949494
"Scale should be a constant power of 2");
94959495

94969496
CSEMap.InsertNode(N, IP);
@@ -9536,7 +9536,7 @@ SDValue SelectionDAG::getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl,
95369536
N->getValue().getValueType().getVectorElementCount()) &&
95379537
"Vector width mismatch between index and data");
95389538
assert(isa<ConstantSDNode>(N->getScale()) &&
9539-
cast<ConstantSDNode>(N->getScale())->getAPIntValue().isPowerOf2() &&
9539+
N->getScale()->getAsAPIntVal().isPowerOf2() &&
95409540
"Scale should be a constant power of 2");
95419541

95429542
CSEMap.InsertNode(N, IP);

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1108,7 +1108,7 @@ bool TargetLowering::SimplifyDemandedBits(
11081108

11091109
if (Op.getOpcode() == ISD::Constant) {
11101110
// We know all of the bits for a constant!
1111-
Known = KnownBits::makeConstant(cast<ConstantSDNode>(Op)->getAPIntValue());
1111+
Known = KnownBits::makeConstant(Op->getAsAPIntVal());
11121112
return false;
11131113
}
11141114

@@ -6350,8 +6350,7 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
63506350
LeadingZeros = DAG.computeKnownBits(N0).countMinLeadingZeros();
63516351
// UnsignedDivisionByConstantInfo doesn't work correctly if leading zeros in
63526352
// the dividend exceeds the leading zeros for the divisor.
6353-
LeadingZeros = std::min(
6354-
LeadingZeros, cast<ConstantSDNode>(N1)->getAPIntValue().countl_zero());
6353+
LeadingZeros = std::min(LeadingZeros, N1->getAsAPIntVal().countl_zero());
63556354
}
63566355

63576356
bool UseNPQ = false, UsePreShift = false, UsePostShift = false;

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2483,7 +2483,7 @@ void AMDGPUDAGToDAGISel::SelectDSAppendConsume(SDNode *N, unsigned IntrID) {
24832483
SDValue PtrBase = Ptr.getOperand(0);
24842484
SDValue PtrOffset = Ptr.getOperand(1);
24852485

2486-
const APInt &OffsetVal = cast<ConstantSDNode>(PtrOffset)->getAPIntValue();
2486+
const APInt &OffsetVal = PtrOffset->getAsAPIntVal();
24872487
if (isDSOffsetLegal(PtrBase, OffsetVal.getZExtValue())) {
24882488
N = glueCopyToM0(N, PtrBase);
24892489
Offset = CurDAG->getTargetConstant(OffsetVal, SDLoc(), MVT::i32);

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2297,7 +2297,7 @@ SDValue NVPTXTargetLowering::LowerBUILD_VECTOR(SDValue Op,
22972297
if (VT == MVT::v2f16 || VT == MVT::v2bf16)
22982298
Value = cast<ConstantFPSDNode>(Operand)->getValueAPF().bitcastToAPInt();
22992299
else if (VT == MVT::v2i16 || VT == MVT::v4i8)
2300-
Value = cast<ConstantSDNode>(Operand)->getAPIntValue();
2300+
Value = Operand->getAsAPIntVal();
23012301
else
23022302
llvm_unreachable("Unsupported type");
23032303
// i8 values are carried around as i16, so we need to zero out upper bits,

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16241,7 +16241,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
1624116241
// Since we are doing this pre-legalize, the RHS can be a constant of
1624216242
// arbitrary bitwidth which may cause issues when trying to get the value
1624316243
// from the underlying APInt.
16244-
auto RHSAPInt = cast<ConstantSDNode>(RHS)->getAPIntValue();
16244+
auto RHSAPInt = RHS->getAsAPIntVal();
1624516245
if (!RHSAPInt.isIntN(64))
1624616246
break;
1624716247

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7023,8 +7023,7 @@ foldBinOpIntoSelectIfProfitable(SDNode *BO, SelectionDAG &DAG,
70237023
if (!NewConstOp)
70247024
return SDValue();
70257025

7026-
const APInt &NewConstAPInt =
7027-
cast<ConstantSDNode>(NewConstOp)->getAPIntValue();
7026+
const APInt &NewConstAPInt = NewConstOp->getAsAPIntVal();
70287027
if (!NewConstAPInt.isZero() && !NewConstAPInt.isAllOnes())
70297028
return SDValue();
70307029

@@ -7154,8 +7153,8 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
71547153
// is SETGE/SETLE to avoid an XORI.
71557154
if (isa<ConstantSDNode>(TrueV) && isa<ConstantSDNode>(FalseV) &&
71567155
CCVal == ISD::SETLT) {
7157-
const APInt &TrueVal = cast<ConstantSDNode>(TrueV)->getAPIntValue();
7158-
const APInt &FalseVal = cast<ConstantSDNode>(FalseV)->getAPIntValue();
7156+
const APInt &TrueVal = TrueV->getAsAPIntVal();
7157+
const APInt &FalseVal = FalseV->getAsAPIntVal();
71597158
if (TrueVal - 1 == FalseVal)
71607159
return DAG.getNode(ISD::ADD, DL, VT, CondV, FalseV);
71617160
if (TrueVal + 1 == FalseVal)

‎llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1649,7 +1649,7 @@ void SystemZDAGToDAGISel::Select(SDNode *Node) {
16491649
}
16501650
}
16511651
if (Node->getValueType(0) == MVT::i128) {
1652-
const APInt &Val = cast<ConstantSDNode>(Node)->getAPIntValue();
1652+
const APInt &Val = Node->getAsAPIntVal();
16531653
SystemZVectorConstantInfo VCI(Val);
16541654
if (VCI.isVectorConstantLegal(*Subtarget)) {
16551655
loadVectorConstant(VCI, Node);

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22551,7 +22551,7 @@ static SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
2255122551
// FIXME: Do this for non-constant compares for constant on LHS?
2255222552
if (CmpVT == MVT::i64 && isa<ConstantSDNode>(Op1) && !isX86CCSigned(X86CC) &&
2255322553
Op0.hasOneUse() && // Hacky way to not break CSE opportunities with sub.
22554-
cast<ConstantSDNode>(Op1)->getAPIntValue().getActiveBits() <= 32 &&
22554+
Op1->getAsAPIntVal().getActiveBits() <= 32 &&
2255522555
DAG.MaskedValueIsZero(Op0, APInt::getHighBitsSet(64, 32))) {
2255622556
CmpVT = MVT::i32;
2255722557
Op0 = DAG.getNode(ISD::TRUNCATE, dl, CmpVT, Op0);
@@ -47029,8 +47029,8 @@ static SDValue combineShiftRightArithmetic(SDNode *N, SelectionDAG &DAG,
4702947029

4703047030
SDValue N00 = N0.getOperand(0);
4703147031
SDValue N01 = N0.getOperand(1);
47032-
APInt ShlConst = (cast<ConstantSDNode>(N01))->getAPIntValue();
47033-
APInt SarConst = (cast<ConstantSDNode>(N1))->getAPIntValue();
47032+
APInt ShlConst = N01->getAsAPIntVal();
47033+
APInt SarConst = N1->getAsAPIntVal();
4703447034
EVT CVT = N1.getValueType();
4703547035

4703647036
if (SarConst.isNegative())

‎llvm/utils/TableGen/CodeGenDAGPatterns.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1368,7 +1368,7 @@ std::string TreePredicateFn::getCodeToRunOnSDNode() const {
13681368
if (immCodeUsesAPFloat())
13691369
Result += "cast<ConstantFPSDNode>(Node)->getValueAPF();\n";
13701370
else if (immCodeUsesAPInt())
1371-
Result += "cast<ConstantSDNode>(Node)->getAPIntValue();\n";
1371+
Result += "Node->getAsAPIntVal();\n";
13721372
else
13731373
Result += "cast<ConstantSDNode>(Node)->getSExtValue();\n";
13741374
return Result + ImmCode;

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