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1 parent 54ea15c commit 2d8e0b2Copy full SHA for 2d8e0b2
llvm/test/Transforms/SLPVectorizer/X86/revec-reduction-logical.ll
@@ -25,3 +25,26 @@ define i1 @logical_and_icmp_diff_preds(<4 x i32> %x) {
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%s3 = select i1 %s2, i1 %c3, i1 false
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ret i1 %s3
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}
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+
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+define i1 @logical_and_icmp_clamp(<4 x i32> %x) {
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+ %x0 = extractelement <4 x i32> %x, i32 0
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+ %x1 = extractelement <4 x i32> %x, i32 1
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+ %x2 = extractelement <4 x i32> %x, i32 2
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+ %x3 = extractelement <4 x i32> %x, i32 3
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+ %c0 = icmp slt i32 %x0, 42
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+ %c1 = icmp slt i32 %x1, 42
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+ %c2 = icmp slt i32 %x2, 42
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+ %c3 = icmp slt i32 %x3, 42
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+ %d0 = icmp sgt i32 %x0, 17
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+ %d1 = icmp sgt i32 %x1, 17
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+ %d2 = icmp sgt i32 %x2, 17
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+ %d3 = icmp sgt i32 %x3, 17
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+ %s1 = select i1 %c0, i1 %c1, i1 false
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+ %s2 = select i1 %s1, i1 %c2, i1 false
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+ %s3 = select i1 %s2, i1 %c3, i1 false
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+ %s4 = select i1 %s3, i1 %d0, i1 false
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+ %s5 = select i1 %s4, i1 %d1, i1 false
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+ %s6 = select i1 %s5, i1 %d2, i1 false
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+ %s7 = select i1 %s6, i1 %d3, i1 false
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+ ret i1 %s7
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+}
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