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XinWang10XinWang10
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[X86][MC] Support Enc/Dec for EGPR for promoted AMX-TILE instruction
1 parent 68f832f commit 2dc0965

16 files changed

+124
-9
lines changed

‎llvm/lib/Target/X86/X86InstrAMX.td

Lines changed: 44 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -14,22 +14,23 @@
1414
//===----------------------------------------------------------------------===//
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// AMX instructions
1616

17-
let Predicates = [HasAMXTILE, In64BitMode] in {
18-
let SchedRW = [WriteSystem] in {
17+
let SchedRW = [WriteSystem] in {
18+
let Predicates = [HasAMXTILE, NoEGPR, In64BitMode] in {
1919
let hasSideEffects = 1,
2020
Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
2121
def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
2222
"ldtilecfg\t$src",
2323
[(int_x86_ldtilecfg addr:$src)]>, VEX, T8;
2424
let hasSideEffects = 1 in
25-
def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src),
26-
"sttilecfg\t$src",
27-
[(int_x86_sttilecfg addr:$src)]>, VEX, T8, PD;
25+
def STTILECFG : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
26+
"sttilecfg\t$src",
27+
[(int_x86_sttilecfg addr:$src)]>,
28+
VEX, T8, PD;
2829
let mayLoad = 1 in
2930
def TILELOADD : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
3031
(ins sibmem:$src),
3132
"tileloadd\t{$src, $dst|$dst, $src}", []>,
32-
VEX, T8, XD;
33+
VEX, T8, XD;
3334
let mayLoad = 1 in
3435
def TILELOADDT1 : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
3536
(ins sibmem:$src),
@@ -42,7 +43,41 @@ let Predicates = [HasAMXTILE, In64BitMode] in {
4243
def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs),
4344
(ins sibmem:$dst, TILE:$src),
4445
"tilestored\t{$src, $dst|$dst, $src}", []>,
45-
VEX, T8, XS;
46+
VEX, T8, XS;
47+
} // HasAMXTILE, NoEGPR
48+
let Predicates = [HasAMXTILE, HasEGPR, In64BitMode] in {
49+
let hasSideEffects = 1,
50+
Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
51+
def LDTILECFG_EVEX : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
52+
"ldtilecfg\t$src",
53+
[(int_x86_ldtilecfg addr:$src)]>,
54+
EVEX, NoCD8, T8, PS;
55+
let hasSideEffects = 1 in
56+
def STTILECFG_EVEX : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
57+
"sttilecfg\t$src",
58+
[(int_x86_sttilecfg addr:$src)]>,
59+
EVEX, NoCD8, T8, PD;
60+
let mayLoad = 1 in
61+
def TILELOADD_EVEX : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
62+
(ins sibmem:$src),
63+
"tileloadd\t{$src, $dst|$dst, $src}", []>,
64+
EVEX, NoCD8, T8, XD;
65+
let mayLoad = 1 in
66+
def TILELOADDT1_EVEX : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
67+
(ins sibmem:$src),
68+
"tileloaddt1\t{$src, $dst|$dst, $src}", []>,
69+
EVEX, NoCD8, T8, PD;
70+
let mayStore = 1 in
71+
def TILESTORED_EVEX : I<0x4b, MRMDestMemFSIB, (outs),
72+
(ins sibmem:$dst, TILE:$src),
73+
"tilestored\t{$src, $dst|$dst, $src}", []>,
74+
EVEX, NoCD8, T8, XS;
75+
} // HasAMXTILE, HasEGPR
76+
let Predicates = [HasAMXTILE, In64BitMode] in {
77+
let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in
78+
def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
79+
"tilerelease", [(int_x86_tilerelease)]>,
80+
VEX, T8, PS;
4681
def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
4782
"tilezero\t$dst", []>,
4883
VEX, T8, XD;
@@ -82,8 +117,8 @@ let Predicates = [HasAMXTILE, In64BitMode] in {
82117
def PTILEZERO : PseudoI<(outs), (ins u8imm:$src),
83118
[(int_x86_tilezero timm:$src)]>;
84119
}
85-
} // SchedRW
86-
} // HasAMXTILE
120+
} // HasAMXTILE
121+
} // SchedRW
87122

88123
let Predicates = [HasAMXINT8, In64BitMode] in {
89124
let SchedRW = [WriteSystem] in {

‎llvm/test/MC/Disassembler/X86/apx/ldtilecfg.txt

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
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# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: ldtilecfg 291(%r28,%r29,4)
5+
# INTEL: ldtilecfg [r28 + 4*r29 + 291]
6+
0x62,0x9a,0x78,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/sttilecfg.txt

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
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# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: sttilecfg 291(%r28,%r29,4)
5+
# INTEL: sttilecfg [r28 + 4*r29 + 291]
6+
0x62,0x9a,0x79,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/tileloadd.txt

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: tileloadd 291(%r28,%r29,4), %tmm6
5+
# INTEL: tileloadd tmm6, [r28 + 4*r29 + 291]
6+
0x62,0x9a,0x7b,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/tileloaddt1.txt

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: tileloaddt1 291(%r28,%r29,4), %tmm6
5+
# INTEL: tileloaddt1 tmm6, [r28 + 4*r29 + 291]
6+
0x62,0x9a,0x79,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/Disassembler/X86/apx/tilestored.txt

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: tilestored %tmm6, 291(%r28,%r29,4)
5+
# INTEL: tilestored [r28 + 4*r29 + 291], tmm6
6+
0x62,0x9a,0x7a,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00

‎llvm/test/MC/X86/apx/ldtilecfg-att.s

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
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3+
# CHECK: ldtilecfg 291(%r28,%r29,4)
4+
# CHECK: encoding: [0x62,0x9a,0x78,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00]
5+
ldtilecfg 291(%r28,%r29,4)

‎llvm/test/MC/X86/apx/ldtilecfg-intel.s

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
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# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: ldtilecfg [r28 + 4*r29 + 291]
4+
# CHECK: encoding: [0x62,0x9a,0x78,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00]
5+
ldtilecfg [r28 + 4*r29 + 291]

‎llvm/test/MC/X86/apx/sttilecfg-att.s

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: sttilecfg 291(%r28,%r29,4)
4+
# CHECK: encoding: [0x62,0x9a,0x79,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00]
5+
sttilecfg 291(%r28,%r29,4)

‎llvm/test/MC/X86/apx/sttilecfg-intel.s

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: sttilecfg [r28 + 4*r29 + 291]
4+
# CHECK: encoding: [0x62,0x9a,0x79,0x08,0x49,0x84,0xac,0x23,0x01,0x00,0x00]
5+
sttilecfg [r28 + 4*r29 + 291]

‎llvm/test/MC/X86/apx/tileloadd-att.s

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: tileloadd 291(%r28,%r29,4), %tmm6
4+
# CHECK: encoding: [0x62,0x9a,0x7b,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
5+
tileloadd 291(%r28,%r29,4), %tmm6

‎llvm/test/MC/X86/apx/tileloadd-intel.s

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
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# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: tileloadd tmm6, [r28 + 4*r29 + 291]
4+
# CHECK: encoding: [0x62,0x9a,0x7b,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
5+
tileloadd tmm6, [r28 + 4*r29 + 291]

‎llvm/test/MC/X86/apx/tileloaddt1-att.s

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
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# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: tileloaddt1 291(%r28,%r29,4), %tmm6
4+
# CHECK: encoding: [0x62,0x9a,0x79,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
5+
tileloaddt1 291(%r28,%r29,4), %tmm6

‎llvm/test/MC/X86/apx/tileloaddt1-intel.s

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: tileloaddt1 tmm6, [r28 + 4*r29 + 291]
4+
# CHECK: encoding: [0x62,0x9a,0x79,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
5+
tileloaddt1 tmm6, [r28 + 4*r29 + 291]

‎llvm/test/MC/X86/apx/tilestored-att.s

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: tilestored %tmm6, 291(%r28,%r29,4)
4+
# CHECK: encoding: [0x62,0x9a,0x7a,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
5+
tilestored %tmm6, 291(%r28,%r29,4)

‎llvm/test/MC/X86/apx/tilestored-intel.s

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
# CHECK: tilestored [r28 + 4*r29 + 291], tmm6
4+
# CHECK: encoding: [0x62,0x9a,0x7a,0x08,0x4b,0xb4,0xac,0x23,0x01,0x00,0x00]
5+
tilestored [r28 + 4*r29 + 291], tmm6

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