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Merge setDefMI into setReg
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-15
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llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -452,7 +452,7 @@ class VSETVLIInfo {
452452

453453
enum : uint8_t {
454454
Uninitialized,
455-
AVLIsReg,
455+
AVLIsDefMI,
456456
AVLIsImm,
457457
AVLIsVLMAX,
458458
AVLIsIgnored,
@@ -481,10 +481,11 @@ class VSETVLIInfo {
481481
void setUnknown() { State = Unknown; }
482482
bool isUnknown() const { return State == Unknown; }
483483

484-
void setAVLReg(Register Reg) {
484+
void setAVLReg(Register Reg, const MachineInstr *DefMI) {
485485
assert(Reg.isVirtual());
486486
AVLReg = Reg;
487-
State = AVLIsReg;
487+
AVLDefMI = DefMI;
488+
State = AVLIsDefMI;
488489
}
489490

490491
void setAVLImm(unsigned Imm) {
@@ -498,7 +499,7 @@ class VSETVLIInfo {
498499
void setAVLDefMI(const MachineInstr *DefMI) { AVLDefMI = DefMI; }
499500

500501
bool hasAVLImm() const { return State == AVLIsImm; }
501-
bool hasAVLReg() const { return State == AVLIsReg; }
502+
bool hasAVLReg() const { return State == AVLIsDefMI; }
502503
bool hasAVLVLMAX() const { return State == AVLIsVLMAX; }
503504
bool hasAVLIgnored() const { return State == AVLIsIgnored; }
504505
Register getAVLReg() const {
@@ -516,10 +517,8 @@ class VSETVLIInfo {
516517
assert(Info.isValid());
517518
if (Info.isUnknown())
518519
setUnknown();
519-
else if (Info.hasAVLReg()) {
520-
setAVLReg(Info.getAVLReg());
521-
setAVLDefMI(Info.getAVLDefMI());
522-
}
520+
else if (Info.hasAVLReg())
521+
setAVLReg(Info.getAVLReg(), Info.getAVLDefMI());
523522
else if (Info.hasAVLVLMAX())
524523
setAVLVLMAX();
525524
else if (Info.hasAVLIgnored())
@@ -879,7 +878,7 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI,
879878
if (AVLReg == RISCV::X0)
880879
NewInfo.setAVLVLMAX();
881880
else
882-
NewInfo.setAVLDefMI(MRI.getVRegDef(AVLReg));
881+
NewInfo.setAVLReg(AVLReg, MRI.getVRegDef(AVLReg));
883882
}
884883
NewInfo.setVTYPE(MI.getOperand(2).getImm());
885884

@@ -951,9 +950,9 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
951950
else
952951
InstrInfo.setAVLImm(Imm);
953952
} else {
954-
InstrInfo.setAVLReg(VLOp.getReg());
955-
if (VLOp.getReg().isVirtual())
956-
InstrInfo.setAVLDefMI(MRI->getVRegDef(VLOp.getReg()));
953+
InstrInfo.setAVLReg(VLOp.getReg(), VLOp.getReg().isVirtual()
954+
? MRI->getVRegDef(VLOp.getReg())
955+
: nullptr);
957956
}
958957
} else {
959958
assert(isScalarExtractInstr(MI));
@@ -1228,9 +1227,10 @@ void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
12281227

12291228
if (RISCV::isFaultFirstLoad(MI)) {
12301229
// Update AVL to vl-output of the fault first load.
1231-
Info.setAVLReg(MI.getOperand(1).getReg());
1232-
if (MI.getOperand(1).getReg().isVirtual())
1233-
Info.setAVLDefMI(MRI->getVRegDef(MI.getOperand(1).getReg()));
1230+
Info.setAVLReg(MI.getOperand(1).getReg(),
1231+
MI.getOperand(1).getReg().isVirtual()
1232+
? MRI->getVRegDef(MI.getOperand(1).getReg())
1233+
: nullptr);
12341234
return;
12351235
}
12361236

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