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michaelmaitlandmichaelmaitland
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[RISCV] Split single width convert to FP pseudos by SEW
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6 files changed

+51
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 37 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -3593,12 +3593,15 @@ multiclass VPseudoConversionRoundingMode<VReg RetClass,
35933593
VReg Op1Class,
35943594
LMULInfo MInfo,
35953595
string Constraint = "",
3596+
int sew = 0,
35963597
int TargetConstraintType = 1> {
35973598
let VLMul = MInfo.value in {
3598-
def "_" # MInfo.MX : VPseudoUnaryNoMaskRoundingMode<RetClass, Op1Class, Constraint, TargetConstraintType>;
3599-
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskRoundingMode<RetClass, Op1Class,
3600-
Constraint, TargetConstraintType>,
3601-
RISCVMaskedPseudo<MaskIdx=2>;
3599+
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
3600+
def suffix : VPseudoUnaryNoMaskRoundingMode<RetClass, Op1Class, Constraint, TargetConstraintType>;
3601+
def suffix # "_MASK" : VPseudoUnaryMaskRoundingMode<RetClass, Op1Class,
3602+
Constraint,
3603+
TargetConstraintType>,
3604+
RISCVMaskedPseudo<MaskIdx=2>;
36023605
}
36033606
}
36043607

@@ -3607,13 +3610,15 @@ multiclass VPseudoConversionRM<VReg RetClass,
36073610
VReg Op1Class,
36083611
LMULInfo MInfo,
36093612
string Constraint = "",
3613+
int sew = 0,
36103614
int TargetConstraintType = 1> {
36113615
let VLMul = MInfo.value in {
3612-
def "_" # MInfo.MX : VPseudoUnaryNoMask_FRM<RetClass, Op1Class,
3613-
Constraint, TargetConstraintType>;
3614-
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_FRM<RetClass, Op1Class,
3615-
Constraint, TargetConstraintType>,
3616-
RISCVMaskedPseudo<MaskIdx=2>;
3616+
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
3617+
def suffix : VPseudoUnaryNoMask_FRM<RetClass, Op1Class,
3618+
Constraint, TargetConstraintType>;
3619+
def suffix # "_MASK" : VPseudoUnaryMask_FRM<RetClass, Op1Class,
3620+
Constraint, TargetConstraintType>,
3621+
RISCVMaskedPseudo<MaskIdx=2>;
36173622
}
36183623
}
36193624

@@ -3660,17 +3665,19 @@ multiclass VPseudoVFROUND_NOEXCEPT_V {
36603665

36613666
multiclass VPseudoVCVTF_V_RM {
36623667
foreach m = MxListF in {
3663-
defm _V : VPseudoConversionRoundingMode<m.vrclass, m.vrclass, m>,
3664-
SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX,
3665-
forceMergeOpRead=true>;
3668+
foreach e = SchedSEWSet<m.MX, isF=1>.val in
3669+
defm _V : VPseudoConversionRoundingMode<m.vrclass, m.vrclass, m, sew=e>,
3670+
SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX, e,
3671+
forceMergeOpRead=true>;
36663672
}
36673673
}
36683674

36693675
multiclass VPseudoVCVTF_RM_V {
36703676
foreach m = MxListF in {
3671-
defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,
3672-
SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX,
3673-
forceMergeOpRead=true>;
3677+
foreach e = SchedSEWSet<m.MX, isF=1>.val in
3678+
defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m, sew=e>,
3679+
SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX, e,
3680+
forceMergeOpRead=true>;
36743681
}
36753682
}
36763683

@@ -4905,14 +4912,17 @@ multiclass VPatConversionTARoundingMode<string intrinsic,
49054912
ValueType result_type,
49064913
ValueType op1_type,
49074914
ValueType mask_type,
4908-
int sew,
4915+
int log2sew,
49094916
LMULInfo vlmul,
49104917
VReg result_reg_class,
4911-
VReg op1_reg_class> {
4918+
VReg op1_reg_class,
4919+
bit isSEWAware = 0> {
49124920
def : VPatUnaryNoMaskRoundingMode<intrinsic, inst, kind, result_type, op1_type,
4913-
sew, vlmul, result_reg_class, op1_reg_class>;
4921+
log2sew, vlmul, result_reg_class,
4922+
op1_reg_class, isSEWAware>;
49144923
def : VPatUnaryMaskRoundingMode<intrinsic, inst, kind, result_type, op1_type,
4915-
mask_type, sew, vlmul, result_reg_class, op1_reg_class>;
4924+
mask_type, log2sew, vlmul, result_reg_class,
4925+
op1_reg_class, isSEWAware>;
49164926
}
49174927

49184928
multiclass VPatBinaryV_VV<string intrinsic, string instruction,
@@ -5905,15 +5915,16 @@ multiclass VPatConversionVI_VF_RM<string intrinsic,
59055915
}
59065916
}
59075917

5908-
multiclass VPatConversionVF_VI_RM<string intrinsic,
5909-
string instruction> {
5918+
multiclass VPatConversionVF_VI_RM<string intrinsic, string instruction,
5919+
bit isSEWAware = 0> {
59105920
foreach fvti = AllFloatVectors in {
59115921
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
59125922
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
59135923
GetVTypePredicates<ivti>.Predicates) in
59145924
defm : VPatConversionTARoundingMode<intrinsic, instruction, "V",
59155925
fvti.Vector, ivti.Vector, fvti.Mask, ivti.Log2SEW,
5916-
ivti.LMul, fvti.RegClass, ivti.RegClass>;
5926+
ivti.LMul, fvti.RegClass, ivti.RegClass,
5927+
isSEWAware>;
59175928
}
59185929
}
59195930

@@ -7269,8 +7280,10 @@ defm : VPatConversionVI_VF_RM<"int_riscv_vfcvt_x_f_v", "PseudoVFCVT_X_F">;
72697280
defm : VPatConversionVI_VF_RM<"int_riscv_vfcvt_xu_f_v", "PseudoVFCVT_XU_F">;
72707281
defm : VPatConversionVI_VF<"int_riscv_vfcvt_rtz_xu_f_v", "PseudoVFCVT_RTZ_XU_F">;
72717282
defm : VPatConversionVI_VF<"int_riscv_vfcvt_rtz_x_f_v", "PseudoVFCVT_RTZ_X_F">;
7272-
defm : VPatConversionVF_VI_RM<"int_riscv_vfcvt_f_x_v", "PseudoVFCVT_F_X">;
7273-
defm : VPatConversionVF_VI_RM<"int_riscv_vfcvt_f_xu_v", "PseudoVFCVT_F_XU">;
7283+
defm : VPatConversionVF_VI_RM<"int_riscv_vfcvt_f_x_v", "PseudoVFCVT_F_X",
7284+
isSEWAware=1>;
7285+
defm : VPatConversionVF_VI_RM<"int_riscv_vfcvt_f_xu_v", "PseudoVFCVT_F_XU",
7286+
isSEWAware=1>;
72747287

72757288
//===----------------------------------------------------------------------===//
72767289
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -410,7 +410,7 @@ multiclass VPatConvertI2FPSDNode_V_RM<SDPatternOperator vop,
410410
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
411411
GetVTypePredicates<ivti>.Predicates) in
412412
def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))),
413-
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
413+
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW)
414414
(fvti.Vector (IMPLICIT_DEF)),
415415
ivti.RegClass:$rs1,
416416
// Value to indicate no rounding mode change in

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1229,7 +1229,7 @@ multiclass VPatConvertI2FPVL_V_RM<SDPatternOperator vop, string instruction_name
12291229
def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
12301230
(ivti.Mask V0),
12311231
VLOpFrag)),
1232-
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
1232+
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
12331233
(fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,
12341234
(ivti.Mask V0),
12351235
// Value to indicate no rounding mode change in
@@ -1247,7 +1247,7 @@ multiclass VPatConvertI2FP_RM_VL_V<SDNode vop, string instruction_name> {
12471247
def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
12481248
(ivti.Mask V0), (XLenVT timm:$frm),
12491249
VLOpFrag)),
1250-
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
1250+
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_MASK")
12511251
(fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,
12521252
(ivti.Mask V0), timm:$frm, GPR:$vl, fvti.Log2SEW, TA_MA)>;
12531253
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -744,14 +744,14 @@ foreach mx = SchedMxListF in {
744744
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
745745
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
746746
defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
747+
defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, sew, IsWorstCase>;
747748
}
748749
}
749750
}
750751
foreach mx = SchedMxList in {
751752
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
752753
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
753754
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
754-
defm "" : LMULWriteResMX<"WriteVFCvtIToFV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
755755
defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;
756756
}
757757
let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
@@ -1179,7 +1179,7 @@ defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
11791179
defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
11801180
defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
11811181
defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
1182-
defm "" : LMULReadAdvance<"ReadVFCvtIToFV", 0>;
1182+
defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
11831183
defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
11841184
defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>;
11851185
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

Lines changed: 5 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -495,36 +495,20 @@ foreach mx = SchedMxListF in {
495495
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
496496
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
497497
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
498-
499-
}
500-
}
501-
}
502-
503-
foreach mx = SchedMxListF in {
504-
foreach sew = SchedSEWSet<mx, isF=1>.val in {
505-
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
506-
defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
507-
let Latency = 6, ReleaseAtCycles = [LMulLat] in {
508498
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
509499
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
510500
}
511-
}
512-
}
513-
foreach mx = SchedMxListF in {
514-
foreach sew = SchedSEWSet<mx, isF=1>.val in {
515-
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
516-
defvar IsWorstCase = SiFiveP600IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
517501
let Latency = 2, ReleaseAtCycles = [LMulLat] in
518502
defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
503+
let Latency = 3, ReleaseAtCycles = [LMulLat] in
504+
defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [SiFiveP600VectorArith], mx, sew, IsWorstCase>;
519505
}
520506
}
521507
foreach mx = SchedMxList in {
522508
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
523509
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
524-
let Latency = 3, ReleaseAtCycles = [LMulLat] in {
525-
defm "" : LMULWriteResMX<"WriteVFCvtIToFV", [SiFiveP600VectorArith], mx, IsWorstCase>;
526-
defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFiveP600VectorArith], mx, IsWorstCase>;
527-
}
510+
let Latency = 3, ReleaseAtCycles = [LMulLat] in
511+
defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFiveP600VectorArith], mx, IsWorstCase>;
528512
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
529513
defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFiveP600VectorArith], mx, IsWorstCase>;
530514
defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFiveP600VectorArith], mx, IsWorstCase>;
@@ -976,7 +960,7 @@ defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
976960
defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
977961
defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
978962
defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
979-
defm "" : LMULReadAdvance<"ReadVFCvtIToFV", 0>;
963+
defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
980964
defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
981965
defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>;
982966
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;

‎llvm/lib/Target/RISCV/RISCVScheduleV.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -449,7 +449,7 @@ defm "" : LMULSchedWrites<"WriteVFMergeV">;
449449
// 13.16. Vector Floating-Point Move Instruction
450450
defm "" : LMULSchedWrites<"WriteVFMovV">;
451451
// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
452-
defm "" : LMULSchedWrites<"WriteVFCvtIToFV">;
452+
defm "" : LMULSEWSchedWritesF<"WriteVFCvtIToFV">;
453453
defm "" : LMULSchedWrites<"WriteVFCvtFToIV">;
454454
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
455455
defm "" : LMULSchedWritesW<"WriteVFWCvtIToFV">;
@@ -675,7 +675,7 @@ defm "" : LMULSchedReads<"ReadVFMergeF">;
675675
// 13.16. Vector Floating-Point Move Instruction
676676
defm "" : LMULSchedReads<"ReadVFMovF">;
677677
// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
678-
defm "" : LMULSchedReads<"ReadVFCvtIToFV">;
678+
defm "" : LMULSEWSchedReadsF<"ReadVFCvtIToFV">;
679679
defm "" : LMULSchedReads<"ReadVFCvtFToIV">;
680680
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
681681
defm "" : LMULSchedReadsW<"ReadVFWCvtIToFV">;
@@ -905,7 +905,7 @@ defm "" : LMULWriteRes<"WriteVFCmpF", []>;
905905
defm "" : LMULWriteRes<"WriteVFClassV", []>;
906906
defm "" : LMULWriteRes<"WriteVFMergeV", []>;
907907
defm "" : LMULWriteRes<"WriteVFMovV", []>;
908-
defm "" : LMULWriteRes<"WriteVFCvtIToFV", []>;
908+
defm "" : LMULSEWWriteResF<"WriteVFCvtIToFV", []>;
909909
defm "" : LMULWriteRes<"WriteVFCvtFToIV", []>;
910910
defm "" : LMULWriteResW<"WriteVFWCvtIToFV", []>;
911911
defm "" : LMULWriteResFW<"WriteVFWCvtFToIV", []>;
@@ -1062,7 +1062,7 @@ defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
10621062
defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
10631063
defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
10641064
defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
1065-
defm "" : LMULReadAdvance<"ReadVFCvtIToFV", 0>;
1065+
defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
10661066
defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
10671067
defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>;
10681068
defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;

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