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AMDGPU: Fix broken check prefix and degraded cov4 test coverage (#131757)
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‎llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v4.ll

Lines changed: 101 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,101 @@
1+
; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes=amdgpu-attributor -o %t.gfx7.bc %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -passes=amdgpu-attributor -o %t.gfx8.bc %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=amdgpu-attributor -o %t.gfx9.bc %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %t.gfx7.bc | FileCheck --check-prefixes=CHECK,PRE-GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %t.gfx8.bc | FileCheck --check-prefixes=CHECK,PRE-GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %t.gfx9.bc | FileCheck --check-prefixes=CHECK,GFX9 %s
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; CHECK: addrspacecast_requires_queue_ptr
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; PRE-GFX9: .amdhsa_user_sgpr_queue_ptr 1
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; GFX9: .amdhsa_user_sgpr_queue_ptr 0
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; CHECK: is_shared_requires_queue_ptr
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; PRE-GFX9: .amdhsa_user_sgpr_queue_ptr 1
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; GFX9: .amdhsa_user_sgpr_queue_ptr 0
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; CHECK: is_private_requires_queue_ptr
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; PRE-GFX9: .amdhsa_user_sgpr_queue_ptr 1
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; GFX9: .amdhsa_user_sgpr_queue_ptr 0
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; CHECK: trap_requires_queue_ptr
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; PRE-GFX9: .amdhsa_user_sgpr_queue_ptr 1
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; GFX9: .amdhsa_user_sgpr_queue_ptr 0
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; CHECK: amdgcn_queue_ptr_requires_queue_ptr
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; CHECK: .amdhsa_user_sgpr_queue_ptr 1
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; On gfx8, the queue ptr is required for this addrspacecast.
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; CHECK: - .args:
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; CHECK-NOT: hidden_queue_ptr
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; CHECK-LABEL: .name: addrspacecast_requires_queue_ptr
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define amdgpu_kernel void @addrspacecast_requires_queue_ptr(ptr addrspace(5) %ptr.private, ptr addrspace(3) %ptr.local) {
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%flat.private = addrspacecast ptr addrspace(5) %ptr.private to ptr
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%flat.local = addrspacecast ptr addrspace(3) %ptr.local to ptr
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store volatile i32 1, ptr %flat.private
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store volatile i32 2, ptr %flat.local
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ret void
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}
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; CHECK: - .args:
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; CHECK-NOT: hidden_shared_base
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; CHECK-LABEL: .name: is_shared_requires_queue_ptr
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define amdgpu_kernel void @is_shared_requires_queue_ptr(ptr %ptr) {
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%is.shared = call i1 @llvm.amdgcn.is.shared(ptr %ptr)
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%zext = zext i1 %is.shared to i32
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store volatile i32 %zext, ptr addrspace(1) poison
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ret void
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}
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; CHECK: - .args:
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; CHECK-NOT: hidden_shared_base
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; CHECK-NOT: hidden_private_base
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; CHECK-NOT: hidden_queue_ptr
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; CHECK-LABEL: .name: is_private_requires_queue_ptr
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define amdgpu_kernel void @is_private_requires_queue_ptr(ptr %ptr) {
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%is.private = call i1 @llvm.amdgcn.is.private(ptr %ptr)
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%zext = zext i1 %is.private to i32
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store volatile i32 %zext, ptr addrspace(1) poison
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ret void
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}
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; CHECK: - .args:
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; CHECK-NOT: hidden_shared_base
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; CHECK-NOT: hidden_private_base
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; CHECK-NOT: hidden_queue_ptr
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; CHECK-LABEL: .name: trap_requires_queue_ptr
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define amdgpu_kernel void @trap_requires_queue_ptr() {
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call void @llvm.trap()
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unreachable
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}
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; CHECK: - .args:
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; CHECK-NOT: hidden_queue_ptr
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; CHECK-NOT: hidden_shared_base
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; CHECK-NOT: hidden_private_base
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; CHECK-LABEL: .name: amdgcn_queue_ptr_requires_queue_ptr
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define amdgpu_kernel void @amdgcn_queue_ptr_requires_queue_ptr(ptr addrspace(1) %ptr) {
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%queue.ptr = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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%dispatch.id = call i64 @llvm.amdgcn.dispatch.id()
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%queue.load = load volatile i8, ptr addrspace(4) %queue.ptr
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%implicitarg.load = load volatile i8, ptr addrspace(4) %implicitarg.ptr
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%dispatch.load = load volatile i8, ptr addrspace(4) %dispatch.ptr
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store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
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ret void
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}
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declare noalias ptr addrspace(4) @llvm.amdgcn.queue.ptr()
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declare noalias ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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declare i64 @llvm.amdgcn.dispatch.id()
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declare noalias ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
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declare i1 @llvm.amdgcn.is.shared(ptr)
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declare i1 @llvm.amdgcn.is.private(ptr)
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declare void @llvm.trap()
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declare void @llvm.debugtrap()
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}

‎llvm/test/CodeGen/AMDGPU/hsa-metadata-queue-ptr-v5.ll

Lines changed: 15 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,18 +1,24 @@
11
; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -passes=amdgpu-attributor -o %t.gfx7.bc %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -passes=amdgpu-attributor -o %t.gfx8.bc %s
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; RUN: opt -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=amdgpu-attributor -o %t.gfx9.bc %s
4-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj < %t.gfx7.bc | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
5-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj < %t.gfx8.bc | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
6-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj < %t.gfx9.bc | llvm-readelf --notes - | FileCheck --check-prefixes=CHECK,GFX9 %s
7-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %t.gfx7.bc | FileCheck --check-prefix=CHECK %s
8-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %t.gfx8.bc | FileCheck --check-prefix=CHECK %s
9-
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %t.gfx9.bc | FileCheck --check-prefixes=CHECK,GFX9 %s
4+
; xUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj < %t.gfx7.bc | llvm-readelf --notes - | FileCheck --check-prefixes=CHECK,PRE-GFX9 %s
5+
; xUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj < %t.gfx8.bc | llvm-readelf --notes - | FileCheck --check-prefixes=CHECK,PRE-GFX9 %s
6+
; xUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj < %t.gfx9.bc | llvm-readelf --notes - | FileCheck --check-prefixes=CHECK,GFX9 %s
7+
; xUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %t.gfx7.bc | FileCheck --check-prefixes=CHECK,PRE-GFX9 %s
8+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %t.gfx8.bc | FileCheck --check-prefixes=CHECK,PRE-GFX9 %s
9+
; xUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %t.gfx9.bc | FileCheck --check-prefixes=CHECK,GFX9 %s
1010

1111

12-
; On gfx8, the queue ptr is required for this addrspacecast.
12+
; On gfx8, the queue ptr is required for this addrspacecast on cov4
1313
; CHECK: - .args:
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; PRE-GFX9: hidden_queue_ptr
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; GFX9-NOT: hidden_queue_ptr
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; PRE-GFX9: .value_kind: hidden_private_base
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; PRE-GFX9: .value_kind: hidden_shared_base
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; GFX9-NOT: hidden_queue_ptr
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; GFX9-NOT: hidden_private_base
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; GFX9-NOT: hidden_shared_base
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1622
; CHECK-LABEL: .name: addrspacecast_requires_queue_ptr
1723
define amdgpu_kernel void @addrspacecast_requires_queue_ptr(ptr addrspace(5) %ptr.private, ptr addrspace(3) %ptr.local) {
1824
%flat.private = addrspacecast ptr addrspace(5) %ptr.private to ptr

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