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[X86] Remove patterns for ADC/SBB with immediate 8 and optimize during MC lowering, NFCI
This is follow-up of D150107.
1 parent d9b84c2 commit 2ef8ae1

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+43
-30
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5 files changed

+43
-30
lines changed

‎llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -424,3 +424,27 @@ bool X86::optimizeToFixedRegisterForm(MCInst &MI) {
424424
MI.addOperand(Saved);
425425
return true;
426426
}
427+
428+
bool X86::optimizeToShortImmediateForm(MCInst &MI) {
429+
unsigned NewOpc;
430+
switch (MI.getOpcode()) {
431+
default:
432+
return false;
433+
FROM_TO(ADC16mi, ADC16mi8)
434+
FROM_TO(ADC16ri, ADC16ri8)
435+
FROM_TO(ADC32mi, ADC32mi8)
436+
FROM_TO(ADC32ri, ADC32ri8)
437+
FROM_TO(ADC64mi32, ADC64mi8)
438+
FROM_TO(ADC64ri32, ADC64ri8)
439+
FROM_TO(SBB16mi, SBB16mi8)
440+
FROM_TO(SBB16ri, SBB16ri8)
441+
FROM_TO(SBB32mi, SBB32mi8)
442+
FROM_TO(SBB32ri, SBB32ri8)
443+
FROM_TO(SBB64mi32, SBB64mi8)
444+
FROM_TO(SBB64ri32, SBB64ri8)
445+
}
446+
if (!isInt<8>(MI.getOperand(MI.getNumOperands() - 1).getImm()))
447+
return false;
448+
MI.setOpcode(NewOpc);
449+
return true;
450+
}

‎llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ bool optimizeMOVSX(MCInst &MI);
2323
bool optimizeINCDEC(MCInst &MI, bool In64BitMode);
2424
bool optimizeMOV(MCInst &MI, bool In64BitMode);
2525
bool optimizeToFixedRegisterForm(MCInst &MI);
26+
bool optimizeToShortImmediateForm(MCInst &MI);
2627
} // namespace X86
2728
} // namespace llvm
2829
#endif

‎llvm/lib/Target/X86/X86InstrArithmetic.td

Lines changed: 14 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -251,14 +251,9 @@ class BinOpRI8_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
251251
[(set typeinfo.RegClass:$dst, EFLAGS,
252252
(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>;
253253

254-
// BinOpRI8_RFF - Binary instructions with inputs "reg, imm8", where the pattern
255-
// has both a regclass and EFLAGS as a result, and has EFLAGS as input.
256-
class BinOpRI8_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
257-
SDPatternOperator opnode, Format f>
258-
: BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), WriteADC,
259-
[(set typeinfo.RegClass:$dst, EFLAGS,
260-
(opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2,
261-
EFLAGS))]>;
254+
// BinOpRI8_RFF - Binary instructions with inputs "reg, imm8".
255+
class BinOpRI8_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, Format f>
256+
: BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), WriteADC, []>;
262257

263258
// BinOpMR - Binary instructions with inputs "[mem], reg".
264259
class BinOpMR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
@@ -362,15 +357,9 @@ class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo,
362357
(implicit EFLAGS)]>,
363358
Sched<[WriteALURMW]>;
364359

365-
// BinOpMI8_RMW_FF - Binary instructions with inputs "[mem], imm8", where the
366-
// pattern sets EFLAGS and implicitly uses EFLAGS.
367-
class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo,
368-
SDPatternOperator opnode, Format f>
369-
: BinOpMI8<mnemonic, typeinfo, f,
370-
[(store (opnode (load addr:$dst),
371-
typeinfo.Imm8Operator:$src, EFLAGS), addr:$dst),
372-
(implicit EFLAGS)]>,
373-
Sched<[WriteADCRMW]>;
360+
// BinOpMI8_RMW_FF - Binary instructions with inputs "[mem], imm8".
361+
class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo, Format f>
362+
: BinOpMI8<mnemonic, typeinfo, f, []>, Sched<[WriteADCRMW]>;
374363

375364
// BinOpMI8_F - Binary instructions with inputs "[mem], imm8", where the pattern
376365
// has EFLAGS as a result.
@@ -979,9 +968,9 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
979968
let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
980969
// NOTE: These are order specific, we want the ri8 forms to be listed
981970
// first so that they are slightly preferred to the ri forms.
982-
def NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, opnode, RegMRM>;
983-
def NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, opnode, RegMRM>;
984-
def NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, opnode, RegMRM>;
971+
def NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, RegMRM>;
972+
def NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, RegMRM>;
973+
def NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, RegMRM>;
985974

986975
def NAME#16ri : BinOpRI_RFF<0x80, mnemonic, Xi16, opnode, RegMRM>;
987976
def NAME#32ri : BinOpRI_RFF<0x80, mnemonic, Xi32, opnode, RegMRM>;
@@ -996,10 +985,10 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
996985

997986
// NOTE: These are order specific, we want the mi8 forms to be listed
998987
// first so that they are slightly preferred to the mi forms.
999-
def NAME#16mi8 : BinOpMI8_RMW_FF<mnemonic, Xi16, opnode, MemMRM>;
1000-
def NAME#32mi8 : BinOpMI8_RMW_FF<mnemonic, Xi32, opnode, MemMRM>;
988+
def NAME#16mi8 : BinOpMI8_RMW_FF<mnemonic, Xi16, MemMRM>;
989+
def NAME#32mi8 : BinOpMI8_RMW_FF<mnemonic, Xi32, MemMRM>;
1001990
let Predicates = [In64BitMode] in
1002-
def NAME#64mi8 : BinOpMI8_RMW_FF<mnemonic, Xi64, opnode, MemMRM>;
991+
def NAME#64mi8 : BinOpMI8_RMW_FF<mnemonic, Xi64, MemMRM>;
1003992

1004993
def NAME#8mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi8 , opnode, MemMRM>;
1005994
def NAME#16mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi16, opnode, MemMRM>;
@@ -1012,9 +1001,9 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
10121001
let Predicates = [Not64BitMode], isCodeGenOnly = 1, ForceDisassemble = 1,
10131002
hasSideEffects = 0 in {
10141003
let Constraints = "$src1 = $dst" in
1015-
def NAME#8ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi8, null_frag, RegMRM>;
1004+
def NAME#8ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi8, RegMRM>;
10161005
let mayLoad = 1, mayStore = 1 in
1017-
def NAME#8mi8 : BinOpMI8_RMW_FF<mnemonic, Xi8, null_frag, MemMRM>;
1006+
def NAME#8mi8 : BinOpMI8_RMW_FF<mnemonic, Xi8, MemMRM>;
10181007
}
10191008
} // Uses = [EFLAGS], Defs = [EFLAGS]
10201009

‎llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4245,13 +4245,11 @@ inline static bool isDefConvertible(const MachineInstr &MI, bool &NoSignFlag,
42454245
case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
42464246
case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
42474247
case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
4248-
case X86::ADC64ri32: case X86::ADC64ri8: case X86::ADC32ri:
4249-
case X86::ADC32ri8: case X86::ADC16ri: case X86::ADC16ri8:
4248+
case X86::ADC64ri32: case X86::ADC32ri: case X86::ADC16ri:
42504249
case X86::ADC8ri: case X86::ADC64rr: case X86::ADC32rr:
42514250
case X86::ADC16rr: case X86::ADC8rr: case X86::ADC64rm:
42524251
case X86::ADC32rm: case X86::ADC16rm: case X86::ADC8rm:
4253-
case X86::SBB64ri32: case X86::SBB64ri8: case X86::SBB32ri:
4254-
case X86::SBB32ri8: case X86::SBB16ri: case X86::SBB16ri8:
4252+
case X86::SBB64ri32: case X86::SBB32ri: case X86::SBB16ri:
42554253
case X86::SBB8ri: case X86::SBB64rr: case X86::SBB32rr:
42564254
case X86::SBB16rr: case X86::SBB8rr: case X86::SBB64rm:
42574255
case X86::SBB32rm: case X86::SBB16rm: case X86::SBB8rm:

‎llvm/lib/Target/X86/X86MCInstLower.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -405,7 +405,8 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
405405
X86::optimizeVPCMPWithImmediateOneOrSix(OutMI) ||
406406
X86::optimizeMOVSX(OutMI) || X86::optimizeINCDEC(OutMI, In64BitMode) ||
407407
X86::optimizeMOV(OutMI, In64BitMode) ||
408-
X86::optimizeToFixedRegisterForm(OutMI))
408+
X86::optimizeToFixedRegisterForm(OutMI) ||
409+
X86::optimizeToShortImmediateForm(OutMI))
409410
return;
410411

411412
// Handle a few special cases to eliminate operand modifiers.

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