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[PowerPC] Add vector conversion builtins to altivec.h - LLVM portion
This patch corresponds to review: https://reviews.llvm.org/D26307 Adds all the intrinsics used for various conversion builtins that will be added to altivec.h. These are type conversions between various types of vectors. llvm-svn: 286596
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‎llvm/include/llvm/IR/IntrinsicsPowerPC.td

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -806,6 +806,30 @@ def int_ppc_vsx_xviexpdp :
806806
def int_ppc_vsx_xviexpsp :
807807
PowerPC_VSX_Intrinsic<"xviexpsp",[llvm_v4f32_ty],
808808
[llvm_v4i32_ty, llvm_v4i32_ty],[IntrNoMem]>;
809+
def int_ppc_vsx_xvcvdpsxws :
810+
PowerPC_VSX_Intrinsic<"xvcvdpsxws", [llvm_v4i32_ty],
811+
[llvm_v2f64_ty], [IntrNoMem]>;
812+
def int_ppc_vsx_xvcvdpuxws :
813+
PowerPC_VSX_Intrinsic<"xvcvdpuxws", [llvm_v4i32_ty],
814+
[llvm_v2f64_ty], [IntrNoMem]>;
815+
def int_ppc_vsx_xvcvsxwdp :
816+
PowerPC_VSX_Intrinsic<"xvcvsxwdp", [llvm_v2f64_ty],
817+
[llvm_v4i32_ty], [IntrNoMem]>;
818+
def int_ppc_vsx_xvcvuxwdp :
819+
PowerPC_VSX_Intrinsic<"xvcvuxwdp", [llvm_v2f64_ty],
820+
[llvm_v4i32_ty], [IntrNoMem]>;
821+
def int_ppc_vsx_xvcvspdp :
822+
PowerPC_VSX_Intrinsic<"xvcvspdp", [llvm_v2f64_ty],
823+
[llvm_v4f32_ty], [IntrNoMem]>;
824+
def int_ppc_vsx_xvcvsxdsp :
825+
PowerPC_VSX_Intrinsic<"xvcvsxdsp", [llvm_v4f32_ty],
826+
[llvm_v2i64_ty], [IntrNoMem]>;
827+
def int_ppc_vsx_xvcvuxdsp :
828+
PowerPC_VSX_Intrinsic<"xvcvuxdsp", [llvm_v4f32_ty],
829+
[llvm_v2i64_ty], [IntrNoMem]>;
830+
def int_ppc_vsx_xvcvdpsp :
831+
PowerPC_VSX_Intrinsic<"xvcvdpsp", [llvm_v4f32_ty],
832+
[llvm_v2f64_ty], [IntrNoMem]>;
809833
}
810834

811835
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -596,25 +596,29 @@ let Uses = [RM] in {
596596

597597
def XVCVDPSP : XX2Form<60, 393,
598598
(outs vsrc:$XT), (ins vsrc:$XB),
599-
"xvcvdpsp $XT, $XB", IIC_VecFP, []>;
599+
"xvcvdpsp $XT, $XB", IIC_VecFP,
600+
[(set v4f32:$XT, (int_ppc_vsx_xvcvdpsp v2f64:$XB))]>;
600601
def XVCVDPSXDS : XX2Form<60, 472,
601602
(outs vsrc:$XT), (ins vsrc:$XB),
602603
"xvcvdpsxds $XT, $XB", IIC_VecFP,
603604
[(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
604605
def XVCVDPSXWS : XX2Form<60, 216,
605606
(outs vsrc:$XT), (ins vsrc:$XB),
606-
"xvcvdpsxws $XT, $XB", IIC_VecFP, []>;
607+
"xvcvdpsxws $XT, $XB", IIC_VecFP,
608+
[(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>;
607609
def XVCVDPUXDS : XX2Form<60, 456,
608610
(outs vsrc:$XT), (ins vsrc:$XB),
609611
"xvcvdpuxds $XT, $XB", IIC_VecFP,
610612
[(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
611613
def XVCVDPUXWS : XX2Form<60, 200,
612614
(outs vsrc:$XT), (ins vsrc:$XB),
613-
"xvcvdpuxws $XT, $XB", IIC_VecFP, []>;
615+
"xvcvdpuxws $XT, $XB", IIC_VecFP,
616+
[(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>;
614617

615618
def XVCVSPDP : XX2Form<60, 457,
616619
(outs vsrc:$XT), (ins vsrc:$XB),
617-
"xvcvspdp $XT, $XB", IIC_VecFP, []>;
620+
"xvcvspdp $XT, $XB", IIC_VecFP,
621+
[(set v2f64:$XT, (int_ppc_vsx_xvcvspdp v4f32:$XB))]>;
618622
def XVCVSPSXDS : XX2Form<60, 408,
619623
(outs vsrc:$XT), (ins vsrc:$XB),
620624
"xvcvspsxds $XT, $XB", IIC_VecFP, []>;
@@ -633,10 +637,12 @@ let Uses = [RM] in {
633637
[(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
634638
def XVCVSXDSP : XX2Form<60, 440,
635639
(outs vsrc:$XT), (ins vsrc:$XB),
636-
"xvcvsxdsp $XT, $XB", IIC_VecFP, []>;
640+
"xvcvsxdsp $XT, $XB", IIC_VecFP,
641+
[(set v4f32:$XT, (int_ppc_vsx_xvcvsxdsp v2i64:$XB))]>;
637642
def XVCVSXWDP : XX2Form<60, 248,
638643
(outs vsrc:$XT), (ins vsrc:$XB),
639-
"xvcvsxwdp $XT, $XB", IIC_VecFP, []>;
644+
"xvcvsxwdp $XT, $XB", IIC_VecFP,
645+
[(set v2f64:$XT, (int_ppc_vsx_xvcvsxwdp v4i32:$XB))]>;
640646
def XVCVSXWSP : XX2Form<60, 184,
641647
(outs vsrc:$XT), (ins vsrc:$XB),
642648
"xvcvsxwsp $XT, $XB", IIC_VecFP,
@@ -647,10 +653,12 @@ let Uses = [RM] in {
647653
[(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
648654
def XVCVUXDSP : XX2Form<60, 424,
649655
(outs vsrc:$XT), (ins vsrc:$XB),
650-
"xvcvuxdsp $XT, $XB", IIC_VecFP, []>;
656+
"xvcvuxdsp $XT, $XB", IIC_VecFP,
657+
[(set v4f32:$XT, (int_ppc_vsx_xvcvuxdsp v2i64:$XB))]>;
651658
def XVCVUXWDP : XX2Form<60, 232,
652659
(outs vsrc:$XT), (ins vsrc:$XB),
653-
"xvcvuxwdp $XT, $XB", IIC_VecFP, []>;
660+
"xvcvuxwdp $XT, $XB", IIC_VecFP,
661+
[(set v2f64:$XT, (int_ppc_vsx_xvcvuxwdp v4i32:$XB))]>;
654662
def XVCVUXWSP : XX2Form<60, 168,
655663
(outs vsrc:$XT), (ins vsrc:$XB),
656664
"xvcvuxwsp $XT, $XB", IIC_VecFP, []>;

‎llvm/test/CodeGen/PowerPC/builtins-ppc-elf2-abi.ll

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -158,6 +158,80 @@ entry:
158158
; CHECK: xvredp {{[0-9]+}}, {{[0-9]+}}
159159
}
160160

161+
; Function Attrs: nounwind readnone
162+
define <4 x i32> @emit_xvcvdpsxws(<2 x double> %a) {
163+
entry:
164+
%0 = tail call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double> %a)
165+
ret <4 x i32> %0
166+
; CHECK-LABEL: @emit_xvcvdpsxws
167+
; CHECK: xvcvdpsxws 34, 34
168+
}
169+
170+
; Function Attrs: nounwind readnone
171+
define <4 x i32> @emit_xvcvdpuxws(<2 x double> %a) {
172+
entry:
173+
%0 = tail call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double> %a)
174+
ret <4 x i32> %0
175+
; CHECK-LABEL: @emit_xvcvdpuxws
176+
; CHECK: xvcvdpuxws 34, 34
177+
}
178+
179+
; Function Attrs: nounwind readnone
180+
define <2 x double> @emit_xvcvsxwdp(<4 x i32> %a) {
181+
entry:
182+
%0 = tail call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> %a)
183+
ret <2 x double> %0
184+
; CHECK-LABEL: @emit_xvcvsxwdp
185+
; CHECK: xvcvsxwdp 34, 34
186+
}
187+
188+
; Function Attrs: nounwind readnone
189+
define <2 x double> @emit_xvcvuxwdp(<4 x i32> %a) {
190+
entry:
191+
%0 = tail call <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32> %a)
192+
ret <2 x double> %0
193+
; CHECK-LABEL: @emit_xvcvuxwdp
194+
; CHECK: xvcvuxwdp 34, 34
195+
}
196+
197+
; Function Attrs: nounwind readnone
198+
define <2 x double> @emit_xvcvspdp(<4 x float> %a) {
199+
entry:
200+
%0 = tail call <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float> %a)
201+
ret <2 x double> %0
202+
; CHECK-LABEL: @emit_xvcvspdp
203+
; CHECK: xvcvspdp 34, 34
204+
}
205+
206+
; Function Attrs: nounwind readnone
207+
define <4 x float> @emit_xvcvsxdsp(<2 x i64> %a) {
208+
entry:
209+
%0 = tail call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> %a)
210+
ret <4 x float> %0
211+
; CHECK-LABEL: @emit_xvcvsxdsp
212+
; CHECK: xvcvsxdsp 34, 34
213+
}
214+
215+
; Function Attrs: nounwind readnone
216+
define <4 x float> @emit_xvcvuxdsp(<2 x i64> %a) {
217+
entry:
218+
%0 = tail call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> %a)
219+
ret <4 x float> %0
220+
; CHECK-LABEL: @emit_xvcvuxdsp
221+
; CHECK: xvcvuxdsp 34, 34
222+
}
223+
224+
; Function Attrs: nounwind readnone
225+
define <4 x float> @emit_xvcvdpsp(<2 x double> %a) {
226+
entry:
227+
%0 = tail call <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double> %a)
228+
ret <4 x float> %0
229+
; CHECK-LABEL: @emit_xvcvdpsp
230+
; CHECK: xvcvdpsp 34, 34
231+
}
232+
233+
; Function Attrs: nounwind readnone
234+
161235
; Function Attrs: nounwind readnone
162236
declare <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>)
163237

@@ -193,3 +267,11 @@ declare <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double>, <2 x double>)
193267

194268
; Function Attrs: nounwind readnone
195269
declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>)
270+
declare <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double>) #1
271+
declare <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>) #1
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declare <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>) #1
273+
declare <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>) #1
274+
declare <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>) #1
275+
declare <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float>) #1
276+
declare <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64>) #1
277+
declare <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64>) #1

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