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5 files changed

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‎llvm/lib/Target/Mips/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter)
1616
tablegen(LLVM MipsGenMCPseudoLowering.inc -gen-pseudo-lowering)
1717
tablegen(LLVM MipsGenRegisterBank.inc -gen-register-bank)
1818
tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
19+
tablegen(LLVM MipsGenSDNodeInfo.inc -gen-sd-node-info)
1920
tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
2021
tablegen(LLVM MipsGenExegesis.inc -gen-exegesis)
2122

‎llvm/lib/Target/Mips/MipsISelLowering.cpp

Lines changed: 0 additions & 122 deletions
Original file line numberDiff line numberDiff line change
@@ -171,128 +171,6 @@ SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
171171
N->getOffset(), Flag);
172172
}
173173

174-
const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
175-
switch ((MipsISD::NodeType)Opcode) {
176-
case MipsISD::FIRST_NUMBER: break;
177-
case MipsISD::JmpLink: return "MipsISD::JmpLink";
178-
case MipsISD::TailCall: return "MipsISD::TailCall";
179-
case MipsISD::Highest: return "MipsISD::Highest";
180-
case MipsISD::Higher: return "MipsISD::Higher";
181-
case MipsISD::Hi: return "MipsISD::Hi";
182-
case MipsISD::Lo: return "MipsISD::Lo";
183-
case MipsISD::GotHi: return "MipsISD::GotHi";
184-
case MipsISD::TlsHi: return "MipsISD::TlsHi";
185-
case MipsISD::GPRel: return "MipsISD::GPRel";
186-
case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
187-
case MipsISD::Ret: return "MipsISD::Ret";
188-
case MipsISD::ERet: return "MipsISD::ERet";
189-
case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
190-
case MipsISD::FAbs: return "MipsISD::FAbs";
191-
case MipsISD::FMS: return "MipsISD::FMS";
192-
case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
193-
case MipsISD::FPCmp: return "MipsISD::FPCmp";
194-
case MipsISD::FSELECT: return "MipsISD::FSELECT";
195-
case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64";
196-
case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
197-
case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
198-
case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
199-
case MipsISD::MFHI: return "MipsISD::MFHI";
200-
case MipsISD::MFLO: return "MipsISD::MFLO";
201-
case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
202-
case MipsISD::Mult: return "MipsISD::Mult";
203-
case MipsISD::Multu: return "MipsISD::Multu";
204-
case MipsISD::MAdd: return "MipsISD::MAdd";
205-
case MipsISD::MAddu: return "MipsISD::MAddu";
206-
case MipsISD::MSub: return "MipsISD::MSub";
207-
case MipsISD::MSubu: return "MipsISD::MSubu";
208-
case MipsISD::DivRem: return "MipsISD::DivRem";
209-
case MipsISD::DivRemU: return "MipsISD::DivRemU";
210-
case MipsISD::DivRem16: return "MipsISD::DivRem16";
211-
case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
212-
case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
213-
case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
214-
case MipsISD::Wrapper: return "MipsISD::Wrapper";
215-
case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
216-
case MipsISD::Sync: return "MipsISD::Sync";
217-
case MipsISD::Ext: return "MipsISD::Ext";
218-
case MipsISD::Ins: return "MipsISD::Ins";
219-
case MipsISD::CIns: return "MipsISD::CIns";
220-
case MipsISD::LWL: return "MipsISD::LWL";
221-
case MipsISD::LWR: return "MipsISD::LWR";
222-
case MipsISD::SWL: return "MipsISD::SWL";
223-
case MipsISD::SWR: return "MipsISD::SWR";
224-
case MipsISD::LDL: return "MipsISD::LDL";
225-
case MipsISD::LDR: return "MipsISD::LDR";
226-
case MipsISD::SDL: return "MipsISD::SDL";
227-
case MipsISD::SDR: return "MipsISD::SDR";
228-
case MipsISD::EXTP: return "MipsISD::EXTP";
229-
case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
230-
case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
231-
case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
232-
case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
233-
case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
234-
case MipsISD::SHILO: return "MipsISD::SHILO";
235-
case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
236-
case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
237-
case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
238-
case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
239-
case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
240-
case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
241-
case MipsISD::DOUBLE_SELECT_I: return "MipsISD::DOUBLE_SELECT_I";
242-
case MipsISD::DOUBLE_SELECT_I64: return "MipsISD::DOUBLE_SELECT_I64";
243-
case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
244-
case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
245-
case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
246-
case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
247-
case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
248-
case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
249-
case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
250-
case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
251-
case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
252-
case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
253-
case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
254-
case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
255-
case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
256-
case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
257-
case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
258-
case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
259-
case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
260-
case MipsISD::MULT: return "MipsISD::MULT";
261-
case MipsISD::MULTU: return "MipsISD::MULTU";
262-
case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
263-
case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
264-
case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
265-
case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
266-
case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
267-
case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
268-
case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
269-
case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
270-
case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
271-
case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
272-
case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
273-
case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
274-
case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
275-
case MipsISD::VCEQ: return "MipsISD::VCEQ";
276-
case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
277-
case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
278-
case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
279-
case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
280-
case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
281-
case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
282-
case MipsISD::VNOR: return "MipsISD::VNOR";
283-
case MipsISD::VSHF: return "MipsISD::VSHF";
284-
case MipsISD::SHF: return "MipsISD::SHF";
285-
case MipsISD::ILVEV: return "MipsISD::ILVEV";
286-
case MipsISD::ILVOD: return "MipsISD::ILVOD";
287-
case MipsISD::ILVL: return "MipsISD::ILVL";
288-
case MipsISD::ILVR: return "MipsISD::ILVR";
289-
case MipsISD::PCKEV: return "MipsISD::PCKEV";
290-
case MipsISD::PCKOD: return "MipsISD::PCKOD";
291-
case MipsISD::INSVE: return "MipsISD::INSVE";
292-
}
293-
return nullptr;
294-
}
295-
296174
MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
297175
const MipsSubtarget &STI)
298176
: TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {

‎llvm/lib/Target/Mips/MipsISelLowering.h

Lines changed: 1 addition & 215 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@
1818
#include "MCTargetDesc/MipsBaseInfo.h"
1919
#include "MCTargetDesc/MipsMCTargetDesc.h"
2020
#include "Mips.h"
21+
#include "MipsSelectionDAGInfo.h"
2122
#include "llvm/CodeGen/CallingConvLower.h"
2223
#include "llvm/CodeGen/ISDOpcodes.h"
2324
#include "llvm/CodeGen/MachineMemOperand.h"
@@ -50,217 +51,6 @@ class MipsTargetMachine;
5051
class TargetLibraryInfo;
5152
class TargetRegisterClass;
5253

53-
namespace MipsISD {
54-
55-
enum NodeType : unsigned {
56-
// Start the numbering from where ISD NodeType finishes.
57-
FIRST_NUMBER = ISD::BUILTIN_OP_END,
58-
59-
// Jump and link (call)
60-
JmpLink,
61-
62-
// Tail call
63-
TailCall,
64-
65-
// Get the Highest (63-48) 16 bits from a 64-bit immediate
66-
Highest,
67-
68-
// Get the Higher (47-32) 16 bits from a 64-bit immediate
69-
Higher,
70-
71-
// Get the High 16 bits from a 32/64-bit immediate
72-
// No relation with Mips Hi register
73-
Hi,
74-
75-
// Get the Lower 16 bits from a 32/64-bit immediate
76-
// No relation with Mips Lo register
77-
Lo,
78-
79-
// Get the High 16 bits from a 32 bit immediate for accessing the GOT.
80-
GotHi,
81-
82-
// Get the High 16 bits from a 32-bit immediate for accessing TLS.
83-
TlsHi,
84-
85-
// Handle gp_rel (small data/bss sections) relocation.
86-
GPRel,
87-
88-
// Thread Pointer
89-
ThreadPointer,
90-
91-
// Vector Floating Point Multiply and Subtract
92-
FMS,
93-
94-
// Floating Point Branch Conditional
95-
FPBrcond,
96-
97-
// Floating Point Compare
98-
FPCmp,
99-
100-
// Floating point Abs
101-
FAbs,
102-
103-
// Floating point select
104-
FSELECT,
105-
106-
// Node used to generate an MTC1 i32 to f64 instruction
107-
MTC1_D64,
108-
109-
// Floating Point Conditional Moves
110-
CMovFP_T,
111-
CMovFP_F,
112-
113-
// FP-to-int truncation node.
114-
TruncIntFP,
115-
116-
// Return
117-
Ret,
118-
119-
// Interrupt, exception, error trap Return
120-
ERet,
121-
122-
// Software Exception Return.
123-
EH_RETURN,
124-
125-
// Node used to extract integer from accumulator.
126-
MFHI,
127-
MFLO,
128-
129-
// Node used to insert integers to accumulator.
130-
MTLOHI,
131-
132-
// Mult nodes.
133-
Mult,
134-
Multu,
135-
136-
// MAdd/Sub nodes
137-
MAdd,
138-
MAddu,
139-
MSub,
140-
MSubu,
141-
142-
// DivRem(u)
143-
DivRem,
144-
DivRemU,
145-
DivRem16,
146-
DivRemU16,
147-
148-
BuildPairF64,
149-
ExtractElementF64,
150-
151-
Wrapper,
152-
153-
DynAlloc,
154-
155-
Sync,
156-
157-
Ext,
158-
Ins,
159-
CIns,
160-
161-
// EXTR.W intrinsic nodes.
162-
EXTP,
163-
EXTPDP,
164-
EXTR_S_H,
165-
EXTR_W,
166-
EXTR_R_W,
167-
EXTR_RS_W,
168-
SHILO,
169-
MTHLIP,
170-
171-
// DPA.W intrinsic nodes.
172-
MULSAQ_S_W_PH,
173-
MAQ_S_W_PHL,
174-
MAQ_S_W_PHR,
175-
MAQ_SA_W_PHL,
176-
MAQ_SA_W_PHR,
177-
DPAU_H_QBL,
178-
DPAU_H_QBR,
179-
DPSU_H_QBL,
180-
DPSU_H_QBR,
181-
DPAQ_S_W_PH,
182-
DPSQ_S_W_PH,
183-
DPAQ_SA_L_W,
184-
DPSQ_SA_L_W,
185-
DPA_W_PH,
186-
DPS_W_PH,
187-
DPAQX_S_W_PH,
188-
DPAQX_SA_W_PH,
189-
DPAX_W_PH,
190-
DPSX_W_PH,
191-
DPSQX_S_W_PH,
192-
DPSQX_SA_W_PH,
193-
MULSA_W_PH,
194-
195-
MULT,
196-
MULTU,
197-
MADD_DSP,
198-
MADDU_DSP,
199-
MSUB_DSP,
200-
MSUBU_DSP,
201-
202-
// DSP shift nodes.
203-
SHLL_DSP,
204-
SHRA_DSP,
205-
SHRL_DSP,
206-
207-
// DSP setcc and select_cc nodes.
208-
SETCC_DSP,
209-
SELECT_CC_DSP,
210-
211-
// Vector comparisons.
212-
// These take a vector and return a boolean.
213-
VALL_ZERO,
214-
VANY_ZERO,
215-
VALL_NONZERO,
216-
VANY_NONZERO,
217-
218-
// These take a vector and return a vector bitmask.
219-
VCEQ,
220-
VCLE_S,
221-
VCLE_U,
222-
VCLT_S,
223-
VCLT_U,
224-
225-
// Vector Shuffle with mask as an operand
226-
VSHF, // Generic shuffle
227-
SHF, // 4-element set shuffle.
228-
ILVEV, // Interleave even elements
229-
ILVOD, // Interleave odd elements
230-
ILVL, // Interleave left elements
231-
ILVR, // Interleave right elements
232-
PCKEV, // Pack even elements
233-
PCKOD, // Pack odd elements
234-
235-
// Vector Lane Copy
236-
INSVE, // Copy element from one vector to another
237-
238-
// Combined (XOR (OR $a, $b), -1)
239-
VNOR,
240-
241-
// Extended vector element extraction
242-
VEXTRACT_SEXT_ELT,
243-
VEXTRACT_ZEXT_ELT,
244-
245-
// Double select nodes for machines without conditional-move.
246-
DOUBLE_SELECT_I,
247-
DOUBLE_SELECT_I64,
248-
249-
// Load/Store Left/Right nodes.
250-
FIRST_MEMORY_OPCODE,
251-
LWL = FIRST_MEMORY_OPCODE,
252-
LWR,
253-
SWL,
254-
SWR,
255-
LDL,
256-
LDR,
257-
SDL,
258-
SDR,
259-
LAST_MEMORY_OPCODE = SDR,
260-
};
261-
262-
} // ene namespace MipsISD
263-
26454
//===--------------------------------------------------------------------===//
26555
// TargetLowering Implementation
26656
//===--------------------------------------------------------------------===//
@@ -331,10 +121,6 @@ class TargetRegisterClass;
331121
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
332122
SelectionDAG &DAG) const override;
333123

334-
/// getTargetNodeName - This method returns the name of a target specific
335-
// DAG node.
336-
const char *getTargetNodeName(unsigned Opcode) const override;
337-
338124
/// getSetCCResultType - get the ISD::SETCC result ValueType
339125
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
340126
EVT VT) const override;

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