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Tim NorthoverTim Northover
Tim Northover
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Tim Northover
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Fix edge cases of ARM shift operands in arith instructions.
As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. llvm-svn: 164456
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-38
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3 files changed

+94
-38
lines changed

‎llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

Lines changed: 6 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -302,11 +302,8 @@ void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
302302
O << getRegisterName(MO1.getReg());
303303

304304
// Print the shift opc.
305-
ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
306-
O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
307-
if (ShOpc == ARM_AM::rrx)
308-
return;
309-
O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
305+
printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
306+
ARM_AM::getSORegOffset(MO2.getImm()));
310307
}
311308

312309

@@ -340,31 +337,6 @@ void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
340337
O << "]";
341338
}
342339

343-
void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
344-
raw_ostream &O) {
345-
const MCOperand &MO1 = MI->getOperand(Op);
346-
const MCOperand &MO2 = MI->getOperand(Op+1);
347-
const MCOperand &MO3 = MI->getOperand(Op+2);
348-
349-
O << "[" << getRegisterName(MO1.getReg()) << "], ";
350-
351-
if (!MO2.getReg()) {
352-
unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
353-
O << '#'
354-
<< ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
355-
<< ImmOffs;
356-
return;
357-
}
358-
359-
O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
360-
<< getRegisterName(MO2.getReg());
361-
362-
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
363-
O << ", "
364-
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
365-
<< " #" << ShImm;
366-
}
367-
368340
void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
369341
raw_ostream &O) {
370342
const MCOperand &MO1 = MI->getOperand(Op);
@@ -392,11 +364,9 @@ void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
392364

393365
const MCOperand &MO3 = MI->getOperand(Op+2);
394366
unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
367+
assert(IdxMode != ARMII::IndexModePost &&
368+
"Should be pre or offset index op");
395369

396-
if (IdxMode == ARMII::IndexModePost) {
397-
printAM2PostIndexOp(MI, Op, O);
398-
return;
399-
}
400370
printAM2PreOrOffsetIndexOp(MI, Op, O);
401371
}
402372

@@ -922,10 +892,8 @@ void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
922892

923893
// Print the shift opc.
924894
assert(MO2.isImm() && "Not a valid t2_so_reg value!");
925-
ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
926-
O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
927-
if (ShOpc != ARM_AM::rrx)
928-
O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
895+
printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
896+
ARM_AM::getSORegOffset(MO2.getImm()));
929897
}
930898

931899
void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,

‎llvm/test/MC/ARM/arm-shift-encoding.s

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,3 +74,46 @@
7474
@ CHECK: ldr r3, [r4], r5 @ encoding: [0x05,0x30,0x94,0xe6]
7575
@ CHECK: str r6, [r7], r8 @ encoding: [0x08,0x60,0x87,0xe6]
7676
@ CHECK: str r9, [r10], r11 @ encoding: [0x0b,0x90,0x8a,0xe6]
77+
78+
@ Uses printSORegImmOperand(), used by ADCrsi ADDrsi ANDrsi BICrsi EORrsi
79+
@ ORRrsi RSBrsi RSCrsi SBCrsi SUBrsi CMNzrsi CMPrsi MOVsi MVNsi TEQrsi TSTrsi
80+
81+
adc sp, lr, pc
82+
adc r1, r8, r9, lsr #32
83+
adc r2, r7, pc, lsr #16
84+
adc r3, r6, r10, lsl #0
85+
adc r4, r5, lr, lsl #16
86+
adc r5, r4, r11, asr #32
87+
adc r6, r3, sp, asr #16
88+
adc r7, r2, r12, rrx
89+
adc r8, r1, r0, ror #16
90+
91+
@ CHECK: adc sp, lr, pc @ encoding: [0x0f,0xd0,0xae,0xe0]
92+
@ CHECK: adc r1, r8, r9, lsr #32 @ encoding: [0x29,0x10,0xa8,0xe0]
93+
@ CHECK: adc r2, r7, pc, lsr #16 @ encoding: [0x2f,0x28,0xa7,0xe0]
94+
@ CHECK: adc r3, r6, r10 @ encoding: [0x0a,0x30,0xa6,0xe0]
95+
@ CHECK: adc r4, r5, lr, lsl #16 @ encoding: [0x0e,0x48,0xa5,0xe0]
96+
@ CHECK: adc r5, r4, r11, asr #32 @ encoding: [0x4b,0x50,0xa4,0xe0]
97+
@ CHECK: adc r6, r3, sp, asr #16 @ encoding: [0x4d,0x68,0xa3,0xe0]
98+
@ CHECK: adc r7, r2, r12, rrx @ encoding: [0x6c,0x70,0xa2,0xe0]
99+
@ CHECK: adc r8, r1, r0, ror #16 @ encoding: [0x60,0x88,0xa1,0xe0]
100+
101+
cmp sp, lr
102+
cmp r1, r8, lsr #32
103+
cmp r2, r7, lsr #16
104+
cmp r3, r6, lsl #0
105+
cmp r4, r5, lsl #16
106+
cmp r5, r4, asr #32
107+
cmp r6, r3, asr #16
108+
cmp r7, r2, rrx
109+
cmp r8, r1, ror #16
110+
111+
@ CHECK: cmp sp, lr @ encoding: [0x0e,0x00,0x5d,0xe1]
112+
@ CHECK: cmp r1, r8, lsr #32 @ encoding: [0x28,0x00,0x51,0xe1]
113+
@ CHECK: cmp r2, r7, lsr #16 @ encoding: [0x27,0x08,0x52,0xe1]
114+
@ CHECK: cmp r3, r6 @ encoding: [0x06,0x00,0x53,0xe1]
115+
@ CHECK: cmp r4, r5, lsl #16 @ encoding: [0x05,0x08,0x54,0xe1]
116+
@ CHECK: cmp r5, r4, asr #32 @ encoding: [0x44,0x00,0x55,0xe1]
117+
@ CHECK: cmp r6, r3, asr #16 @ encoding: [0x43,0x08,0x56,0xe1]
118+
@ CHECK: cmp r7, r2, rrx @ encoding: [0x62,0x00,0x57,0xe1]
119+
@ CHECK: cmp r8, r1, ror #16 @ encoding: [0x61,0x08,0x58,0xe1]

‎llvm/test/MC/ARM/thumb-shift-encoding.s

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7 -show-encoding < %s | FileCheck %s
2+
3+
@ Uses printT2SOOperand(), used by t2ADCrs t2ADDrs t2ANDrs t2BICrs t2EORrs
4+
@ t2ORNrs t2ORRrs t2RSBrs t2SBCrs t2SUBrs t2CMNzrs t2CMPrs t2MOVSsi t2MOVsi
5+
@ t2MVNs t2TEQrs t2TSTrs
6+
7+
sbc.w r12, lr, r0
8+
sbc.w r1, r8, r9, lsr #32
9+
sbc.w r2, r7, pc, lsr #16
10+
sbc.w r3, r6, r10, lsl #0
11+
sbc.w r4, r5, lr, lsl #16
12+
sbc.w r5, r4, r11, asr #32
13+
sbc.w r6, r3, sp, asr #16
14+
sbc.w r7, r2, r12, rrx
15+
sbc.w r8, r1, r0, ror #16
16+
17+
@ CHECK: sbc.w r12, lr, r0 @ encoding: [0x6e,0xeb,0x00,0x0c]
18+
@ CHECK: sbc.w r1, r8, r9, lsr #32 @ encoding: [0x68,0xeb,0x19,0x01]
19+
@ CHECK: sbc.w r2, r7, pc, lsr #16 @ encoding: [0x67,0xeb,0x1f,0x42]
20+
@ CHECK: sbc.w r3, r6, r10 @ encoding: [0x66,0xeb,0x0a,0x03]
21+
@ CHECK: sbc.w r4, r5, lr, lsl #16 @ encoding: [0x65,0xeb,0x0e,0x44]
22+
@ CHECK: sbc.w r5, r4, r11, asr #32 @ encoding: [0x64,0xeb,0x2b,0x05]
23+
@ CHECK: sbc.w r6, r3, sp, asr #16 @ encoding: [0x63,0xeb,0x2d,0x46]
24+
@ CHECK: sbc.w r7, r2, r12, rrx @ encoding: [0x62,0xeb,0x3c,0x07]
25+
@ CHECK: sbc.w r8, r1, r0, ror #16 @ encoding: [0x61,0xeb,0x30,0x48]
26+
27+
and.w r12, lr, r0
28+
and.w r1, r8, r9, lsr #32
29+
and.w r2, r7, pc, lsr #16
30+
and.w r3, r6, r10, lsl #0
31+
and.w r4, r5, lr, lsl #16
32+
and.w r5, r4, r11, asr #32
33+
and.w r6, r3, sp, asr #16
34+
and.w r7, r2, r12, rrx
35+
and.w r8, r1, r0, ror #16
36+
37+
@ CHECK: and.w r12, lr, r0 @ encoding: [0x0e,0xea,0x00,0x0c]
38+
@ CHECK: and.w r1, r8, r9, lsr #32 @ encoding: [0x08,0xea,0x19,0x01]
39+
@ CHECK: and.w r2, r7, pc, lsr #16 @ encoding: [0x07,0xea,0x1f,0x42]
40+
@ CHECK: and.w r3, r6, r10 @ encoding: [0x06,0xea,0x0a,0x03]
41+
@ CHECK: and.w r4, r5, lr, lsl #16 @ encoding: [0x05,0xea,0x0e,0x44]
42+
@ CHECK: and.w r5, r4, r11, asr #32 @ encoding: [0x04,0xea,0x2b,0x05]
43+
@ CHECK: and.w r6, r3, sp, asr #16 @ encoding: [0x03,0xea,0x2d,0x46]
44+
@ CHECK: and.w r7, r2, r12, rrx @ encoding: [0x02,0xea,0x3c,0x07]
45+
@ CHECK: and.w r8, r1, r0, ror #16 @ encoding: [0x01,0xea,0x30,0x48]

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