Skip to content

Commit 2fe8466

Browse files
author
Zoran Jovanovic
committed
[mips][microMIPS] Implement DDIV, DMOD, DDIVU and DMODU instructions
Differential Revision: http://reviews.llvm.org/D10953 llvm-svn: 245297
1 parent d5a00e8 commit 2fe8466

File tree

5 files changed

+72
-0
lines changed

5 files changed

+72
-0
lines changed

‎llvm/lib/Target/Mips/MicroMips64r6InstrFormats.td

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -68,3 +68,19 @@ class POOL32S_DALIGN_FM_MMR6 {
6868
let Inst{7-6} = 0b00;
6969
let Inst{5-0} = 0b011100;
7070
}
71+
72+
class POOL32A_DIVMOD_FM_MMR6<string instr_asm, bits<9> funct>
73+
: MMR6Arch<instr_asm> {
74+
bits<5> rd;
75+
bits<5> rs;
76+
bits<5> rt;
77+
78+
bits<32> Inst;
79+
80+
let Inst{31-26} = 0b010110;
81+
let Inst{25-21} = rd;
82+
let Inst{20-16} = rs;
83+
let Inst{15-11} = rt;
84+
let Inst{10-9} = 0b00;
85+
let Inst{8-0} = funct;
86+
}

‎llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,10 @@ class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
2424
class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
2525
class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
2626
class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
27+
class DDIV_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddiv", 0b100011000>;
28+
class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>;
29+
class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
30+
class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
2731

2832
//===----------------------------------------------------------------------===//
2933
//
@@ -77,6 +81,11 @@ class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
7781

7882
class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
7983

84+
class DDIV_MM64R6_DESC : ArithLogicR<"ddiv", GPR32Opnd>;
85+
class DMOD_MM64R6_DESC : ArithLogicR<"dmod", GPR32Opnd>;
86+
class DDIVU_MM64R6_DESC : ArithLogicR<"ddivu", GPR32Opnd>;
87+
class DMODU_MM64R6_DESC : ArithLogicR<"dmodu", GPR32Opnd>;
88+
8089
//===----------------------------------------------------------------------===//
8190
//
8291
// Instruction Definitions
@@ -95,4 +104,12 @@ let DecoderNamespace = "MicroMipsR6" in {
95104
ISA_MICROMIPS64R6;
96105
def DALIGN_MM64R6 : StdMMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
97106
ISA_MICROMIPS64R6;
107+
def DDIV_MM64R6 : R6MMR6Rel, DDIV_MM64R6_DESC, DDIV_MM64R6_ENC,
108+
ISA_MICROMIPS64R6;
109+
def DMOD_MM64R6 : R6MMR6Rel, DMOD_MM64R6_DESC, DMOD_MM64R6_ENC,
110+
ISA_MICROMIPS64R6;
111+
def DDIVU_MM64R6 : R6MMR6Rel, DDIVU_MM64R6_DESC, DDIVU_MM64R6_ENC,
112+
ISA_MICROMIPS64R6;
113+
def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
114+
ISA_MICROMIPS64R6;
98115
}

‎llvm/test/MC/Disassembler/Mips/micromips64r6.txt

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,3 +13,11 @@
1313
0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 3, 7
1414

1515
0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5
16+
17+
0x58 0x64 0x29 0x18 # CHECK: ddiv $3, $4, $5
18+
19+
0x58 0x64 0x29 0x58 # CHECK: dmod $3, $4, $5
20+
21+
0x58 0x64 0x29 0x98 # CHECK: ddivu $3, $4, $5
22+
23+
0x58 0x64 0x29 0xd8 # CHECK: dmodu $3, $4, $5

‎llvm/test/MC/Mips/micromips64r6/invalid.s

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips64r6 -mattr=micromips 2>%t1
2+
# RUN: FileCheck %s < %t1
3+
4+
ddiv $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
5+
ddiv $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
6+
ddiv $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
7+
dmod $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
8+
dmod $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9+
dmod $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10+
ddivu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
11+
ddivu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
12+
ddivu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
13+
dmodu $32, $4, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
14+
dmodu $3, $34, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
15+
dmodu $3, $4, $35 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction

‎llvm/test/MC/Mips/micromips64r6/valid.s

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 -mattr=micromips | FileCheck %s
2+
a:
3+
.set noat
4+
daui $3, $4, 5 # CHECK: daui $3, $4, 5 # encoding: [0xf0,0x64,0x00,0x05]
5+
dahi $3, 4 # CHECK: dahi $3, 4 # encoding: [0x42,0x23,0x00,0x04]
6+
dati $3, 4 # CHECK: dati $3, 4 # encoding: [0x42,0x03,0x00,0x04]
7+
dext $9, $6, 3, 7 # CHECK: dext $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xec]
8+
dextm $9, $6, 3, 7 # CHECK: dextm $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xe4]
9+
dextu $9, $6, 3, 7 # CHECK: dextu $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xd4]
10+
dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c]
11+
ddiv $3, $4, $5 # CHECK: ddiv $3, $4, $5 # encoding: [0x58,0x64,0x29,0x18]
12+
dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0x64,0x29,0x58]
13+
ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0x64,0x29,0x98]
14+
dmodu $3, $4, $5 # CHECK: dmodu $3, $4, $5 # encoding: [0x58,0x64,0x29,0xd8]
15+
16+
1:

0 commit comments

Comments
 (0)