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[X86][NFC] Refine code in X86InstrArithmetic.td
1. Simplify the variable name 2. Change HasOddOpcode to HasEvenOpcode b/c a. opcode of any 8-bit arithmetic instruction is even b. opcode of a 16/32/64-bit arithmetic instruction is usually odd, but it can be even sometimes, e.g. INC/DEC, ADCX/ADOX c. so that we can remove `let Opcode = o` for the mentioned corner cases.
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‎llvm/lib/Target/X86/X86InstrArithmetic.td

Lines changed: 67 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -232,7 +232,7 @@ class BinOpMIF_MF<bits<8> o, string m, X86TypeInfo t, SDNode node, Format f>
232232

233233
// BinOpMI8 - Instructions that read "[mem], imm8".
234234
class BinOpMI8<string m, X86TypeInfo t, Format f>
235-
: ITy<0x82, f, t, (outs), (ins t.MemOperand:$dst, t.Imm8Operand:$src), m,
235+
: ITy<0x83, f, t, (outs), (ins t.MemOperand:$dst, t.Imm8Operand:$src), m,
236236
"{$src, $dst|$dst, $src}", []> {
237237
let ImmT = Imm8;
238238
let mayLoad = 1;
@@ -292,15 +292,15 @@ class UnaryOpM<bits<8> o, Format f, string m, X86TypeInfo t, list<dag> p>
292292

293293
// INCDECR - Instructions like "inc reg".
294294
class INCDECR<Format f, string m, X86TypeInfo t, SDPatternOperator node>
295-
: UnaryOpR<0xFE, f, m, t,
295+
: UnaryOpR<0xFF, f, m, t,
296296
[(set t.RegClass:$dst, EFLAGS, (node t.RegClass:$src1, 1))]>,
297297
DefEFLAGS {
298298
let isConvertibleToThreeAddress = 1; // Can xform into LEA.
299299
}
300300

301301
// INCDECM - Instructions like "inc [mem]".
302302
class INCDECM<Format f, string m, X86TypeInfo t, int num>
303-
: UnaryOpM<0xFE, f, m, t,
303+
: UnaryOpM<0xFF, f, m, t,
304304
[(store (add (t.LoadNode addr:$dst), num), addr:$dst),
305305
(implicit EFLAGS)]>, DefEFLAGS;
306306

@@ -309,7 +309,6 @@ class INCDECR_ALT<bits<8> o, string m, X86TypeInfo t>
309309
: UnaryOpR<o, AddRegFrm, m, t, []>, DefEFLAGS {
310310
// Short forms only valid in 32-bit mode. Selected during MCInst lowering.
311311
let Predicates = [Not64BitMode];
312-
let Opcode = o;
313312
}
314313

315314
// MulOpR - Instructions like "mul reg".
@@ -664,13 +663,13 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
664663
def NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>;
665664
// NOTE: These are order specific, we want the ri8 forms to be listed
666665
// first so that they are slightly preferred to the ri forms.
667-
def NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, RegMRM>;
668-
def NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, RegMRM>;
669-
def NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, RegMRM>;
666+
def NAME#16ri8 : BinOpRI8_RF<0x83, mnemonic, Xi16, RegMRM>;
667+
def NAME#32ri8 : BinOpRI8_RF<0x83, mnemonic, Xi32, RegMRM>;
668+
def NAME#64ri8 : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM>;
670669

671-
def NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>;
672-
def NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>;
673-
def NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>;
670+
def NAME#16ri : BinOpRI_RF<0x81, mnemonic, Xi16, opnodeflag, RegMRM>;
671+
def NAME#32ri : BinOpRI_RF<0x81, mnemonic, Xi32, opnodeflag, RegMRM>;
672+
def NAME#64ri32: BinOpRI_RF<0x81, mnemonic, Xi64, opnodeflag, RegMRM>;
674673
}
675674
} // Constraints = "$src1 = $dst"
676675

@@ -687,10 +686,10 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
687686
def NAME#64mi8 : BinOpMI8_MF<mnemonic, Xi64, MemMRM>;
688687

689688
def NAME#8mi : BinOpMI_MF<0x80, mnemonic, Xi8 , opnode, MemMRM>;
690-
def NAME#16mi : BinOpMI_MF<0x80, mnemonic, Xi16, opnode, MemMRM>;
691-
def NAME#32mi : BinOpMI_MF<0x80, mnemonic, Xi32, opnode, MemMRM>;
689+
def NAME#16mi : BinOpMI_MF<0x81, mnemonic, Xi16, opnode, MemMRM>;
690+
def NAME#32mi : BinOpMI_MF<0x81, mnemonic, Xi32, opnode, MemMRM>;
692691
let Predicates = [In64BitMode] in
693-
def NAME#64mi32 : BinOpMI_MF<0x80, mnemonic, Xi64, opnode, MemMRM>;
692+
def NAME#64mi32 : BinOpMI_MF<0x81, mnemonic, Xi64, opnode, MemMRM>;
694693

695694
// These are for the disassembler since 0x82 opcode behaves like 0x80, but
696695
// not in 64-bit mode.
@@ -744,13 +743,13 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
744743
let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
745744
// NOTE: These are order specific, we want the ri8 forms to be listed
746745
// first so that they are slightly preferred to the ri forms.
747-
def NAME#16ri8 : BinOpRI8F_RF<0x82, mnemonic, Xi16, RegMRM>;
748-
def NAME#32ri8 : BinOpRI8F_RF<0x82, mnemonic, Xi32, RegMRM>;
749-
def NAME#64ri8 : BinOpRI8F_RF<0x82, mnemonic, Xi64, RegMRM>;
746+
def NAME#16ri8 : BinOpRI8F_RF<0x83, mnemonic, Xi16, RegMRM>;
747+
def NAME#32ri8 : BinOpRI8F_RF<0x83, mnemonic, Xi32, RegMRM>;
748+
def NAME#64ri8 : BinOpRI8F_RF<0x83, mnemonic, Xi64, RegMRM>;
750749

751-
def NAME#16ri : BinOpRIF_RF<0x80, mnemonic, Xi16, opnode, RegMRM>;
752-
def NAME#32ri : BinOpRIF_RF<0x80, mnemonic, Xi32, opnode, RegMRM>;
753-
def NAME#64ri32: BinOpRIF_RF<0x80, mnemonic, Xi64, opnode, RegMRM>;
750+
def NAME#16ri : BinOpRIF_RF<0x81, mnemonic, Xi16, opnode, RegMRM>;
751+
def NAME#32ri : BinOpRIF_RF<0x81, mnemonic, Xi32, opnode, RegMRM>;
752+
def NAME#64ri32: BinOpRIF_RF<0x81, mnemonic, Xi64, opnode, RegMRM>;
754753
}
755754
} // Constraints = "$src1 = $dst"
756755

@@ -767,10 +766,10 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
767766
def NAME#64mi8 : BinOpMI8F_MF<mnemonic, Xi64, MemMRM>;
768767

769768
def NAME#8mi : BinOpMIF_MF<0x80, mnemonic, Xi8 , opnode, MemMRM>;
770-
def NAME#16mi : BinOpMIF_MF<0x80, mnemonic, Xi16, opnode, MemMRM>;
771-
def NAME#32mi : BinOpMIF_MF<0x80, mnemonic, Xi32, opnode, MemMRM>;
769+
def NAME#16mi : BinOpMIF_MF<0x81, mnemonic, Xi16, opnode, MemMRM>;
770+
def NAME#32mi : BinOpMIF_MF<0x81, mnemonic, Xi32, opnode, MemMRM>;
772771
let Predicates = [In64BitMode] in
773-
def NAME#64mi32 : BinOpMIF_MF<0x80, mnemonic, Xi64, opnode, MemMRM>;
772+
def NAME#64mi32 : BinOpMIF_MF<0x81, mnemonic, Xi64, opnode, MemMRM>;
774773

775774
// These are for the disassembler since 0x82 opcode behaves like 0x80, but
776775
// not in 64-bit mode.
@@ -822,13 +821,13 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
822821
let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
823822
// NOTE: These are order specific, we want the ri8 forms to be listed
824823
// first so that they are slightly preferred to the ri forms.
825-
def NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, RegMRM>;
826-
def NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, RegMRM>;
827-
def NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, RegMRM>;
824+
def NAME#16ri8 : BinOpRI8_F<0x83, mnemonic, Xi16, RegMRM>;
825+
def NAME#32ri8 : BinOpRI8_F<0x83, mnemonic, Xi32, RegMRM>;
826+
def NAME#64ri8 : BinOpRI8_F<0x83, mnemonic, Xi64, RegMRM>;
828827

829-
def NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>;
830-
def NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>;
831-
def NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>;
828+
def NAME#16ri : BinOpRI_F<0x81, mnemonic, Xi16, opnode, RegMRM>;
829+
def NAME#32ri : BinOpRI_F<0x81, mnemonic, Xi32, opnode, RegMRM>;
830+
def NAME#64ri32: BinOpRI_F<0x81, mnemonic, Xi64, opnode, RegMRM>;
832831
}
833832

834833
def NAME#8mr : BinOpMR_F<BaseOpc, mnemonic, Xi8 , opnode>;
@@ -844,10 +843,10 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
844843
def NAME#64mi8 : BinOpMI8_F<mnemonic, Xi64, MemMRM>;
845844

846845
def NAME#8mi : BinOpMI_F<0x80, mnemonic, Xi8 , opnode, MemMRM>;
847-
def NAME#16mi : BinOpMI_F<0x80, mnemonic, Xi16, opnode, MemMRM>;
848-
def NAME#32mi : BinOpMI_F<0x80, mnemonic, Xi32, opnode, MemMRM>;
846+
def NAME#16mi : BinOpMI_F<0x81, mnemonic, Xi16, opnode, MemMRM>;
847+
def NAME#32mi : BinOpMI_F<0x81, mnemonic, Xi32, opnode, MemMRM>;
849848
let Predicates = [In64BitMode] in
850-
def NAME#64mi32 : BinOpMI_F<0x80, mnemonic, Xi64, opnode, MemMRM>;
849+
def NAME#64mi32 : BinOpMI_F<0x81, mnemonic, Xi64, opnode, MemMRM>;
851850

852851
// These are for the disassembler since 0x82 opcode behaves like 0x80, but
853852
// not in 64-bit mode.
@@ -868,16 +867,16 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
868867
}
869868

870869

871-
defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
870+
defm AND : ArithBinOp_RF<0x21, 0x23, 0x25, "and", MRM4r, MRM4m,
872871
X86and_flag, and, 1, 0, 0>;
873-
defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
872+
defm OR : ArithBinOp_RF<0x09, 0x0B, 0x0D, "or", MRM1r, MRM1m,
874873
X86or_flag, or, 1, 0, 0>;
875-
defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m,
874+
defm XOR : ArithBinOp_RF<0x31, 0x33, 0x35, "xor", MRM6r, MRM6m,
876875
X86xor_flag, xor, 1, 0, 0>;
877-
defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m,
876+
defm ADD : ArithBinOp_RF<0x01, 0x03, 0x05, "add", MRM0r, MRM0m,
878877
X86add_flag, add, 1, 1, 1>;
879878
let isCompare = 1 in {
880-
defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
879+
defm SUB : ArithBinOp_RF<0x29, 0x2B, 0x2D, "sub", MRM5r, MRM5m,
881880
X86sub_flag, sub, 0, 1, 0>;
882881
}
883882

@@ -891,13 +890,13 @@ def XOR8rr_NOREX : I<0x30, MRMDestReg, (outs GR8_NOREX:$dst),
891890
Sched<[WriteALU]>;
892891

893892
// Arithmetic.
894-
defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag,
893+
defm ADC : ArithBinOp_RFF<0x11, 0x13, 0x15, "adc", MRM2r, MRM2m, X86adc_flag,
895894
1, 0>;
896-
defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag,
895+
defm SBB : ArithBinOp_RFF<0x19, 0x1B, 0x1D, "sbb", MRM3r, MRM3m, X86sbb_flag,
897896
0, 0>;
898897

899898
let isCompare = 1 in {
900-
defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
899+
defm CMP : ArithBinOp_F<0x39, 0x3B, 0x3D, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
901900
}
902901

903902
// Patterns to recognize loads on the LHS of an ADC. We can't make X86adc_flag
@@ -1040,32 +1039,32 @@ let isCompare = 1 in {
10401039
// combine them. This gives bunch of other patterns that start with
10411040
// and a chance to match.
10421041
def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , null_frag>;
1043-
def TEST16rr : BinOpRR_F<0x84, "test", Xi16, null_frag>;
1044-
def TEST32rr : BinOpRR_F<0x84, "test", Xi32, null_frag>;
1045-
def TEST64rr : BinOpRR_F<0x84, "test", Xi64, null_frag>;
1042+
def TEST16rr : BinOpRR_F<0x85, "test", Xi16, null_frag>;
1043+
def TEST32rr : BinOpRR_F<0x85, "test", Xi32, null_frag>;
1044+
def TEST64rr : BinOpRR_F<0x85, "test", Xi64, null_frag>;
10461045
} // isCommutable
10471046

10481047
def TEST8mr : BinOpMR_F<0x84, "test", Xi8 , null_frag>;
1049-
def TEST16mr : BinOpMR_F<0x84, "test", Xi16, null_frag>;
1050-
def TEST32mr : BinOpMR_F<0x84, "test", Xi32, null_frag>;
1051-
def TEST64mr : BinOpMR_F<0x84, "test", Xi64, null_frag>;
1048+
def TEST16mr : BinOpMR_F<0x85, "test", Xi16, null_frag>;
1049+
def TEST32mr : BinOpMR_F<0x85, "test", Xi32, null_frag>;
1050+
def TEST64mr : BinOpMR_F<0x85, "test", Xi64, null_frag>;
10521051

10531052
def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>;
1054-
def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>;
1055-
def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>;
1056-
def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>;
1053+
def TEST16ri : BinOpRI_F<0xF7, "test", Xi16, X86testpat, MRM0r>;
1054+
def TEST32ri : BinOpRI_F<0xF7, "test", Xi32, X86testpat, MRM0r>;
1055+
def TEST64ri32 : BinOpRI_F<0xF7, "test", Xi64, X86testpat, MRM0r>;
10571056

10581057
def TEST8mi : BinOpMI_F<0xF6, "test", Xi8 , X86testpat, MRM0m>;
1059-
def TEST16mi : BinOpMI_F<0xF6, "test", Xi16, X86testpat, MRM0m>;
1060-
def TEST32mi : BinOpMI_F<0xF6, "test", Xi32, X86testpat, MRM0m>;
1058+
def TEST16mi : BinOpMI_F<0xF7, "test", Xi16, X86testpat, MRM0m>;
1059+
def TEST32mi : BinOpMI_F<0xF7, "test", Xi32, X86testpat, MRM0m>;
10611060

10621061
let Predicates = [In64BitMode] in
1063-
def TEST64mi32 : BinOpMI_F<0xF6, "test", Xi64, X86testpat, MRM0m>;
1062+
def TEST64mi32 : BinOpMI_F<0xF7, "test", Xi64, X86testpat, MRM0m>;
10641063

10651064
def TEST8i8 : BinOpAI_F<0xA8, "test", Xi8 , AL, "{$src, %al|al, $src}">;
1066-
def TEST16i16 : BinOpAI_F<0xA8, "test", Xi16, AX, "{$src, %ax|ax, $src}">;
1067-
def TEST32i32 : BinOpAI_F<0xA8, "test", Xi32, EAX, "{$src, %eax|eax, $src}">;
1068-
def TEST64i32 : BinOpAI_F<0xA8, "test", Xi64, RAX, "{$src, %rax|rax, $src}">;
1065+
def TEST16i16 : BinOpAI_F<0xA9, "test", Xi16, AX, "{$src, %ax|ax, $src}">;
1066+
def TEST32i32 : BinOpAI_F<0xA9, "test", Xi32, EAX, "{$src, %eax|eax, $src}">;
1067+
def TEST64i32 : BinOpAI_F<0xA9, "test", Xi64, RAX, "{$src, %rax|rax, $src}">;
10691068
} // isCompare
10701069

10711070
// Patterns to match a relocImm into the immediate field.
@@ -1189,38 +1188,35 @@ let Uses = [RDX] in
11891188
//
11901189
// We don't have patterns for these as there is no advantage over ADC for
11911190
// most code.
1192-
class ADCOXOpRR <bits<8> opcode, string mnemonic, X86TypeInfo info>
1193-
: BinOpRR_RF<opcode, mnemonic, info, null_frag> {
1194-
let Opcode = opcode;
1191+
class ADCOXOpRR <string m, X86TypeInfo t>
1192+
: BinOpRR_RF<0xF6, m, t, null_frag> {
11951193
let OpSize = OpSizeFixed;
11961194
let Form = MRMSrcReg;
1195+
let isCommutable = 1;
11971196
}
11981197

1199-
class ADCOXOpRM <bits<8> opcode, string mnemonic, X86TypeInfo info>
1200-
: BinOpRM_RF<opcode, mnemonic, info, null_frag> {
1201-
let Opcode = opcode;
1198+
class ADCOXOpRM <string m, X86TypeInfo t>
1199+
: BinOpRM_RF<0xF6, m, t, null_frag> {
12021200
let OpSize = OpSizeFixed;
12031201
let Form = MRMSrcMem;
12041202
}
12051203

12061204
let Predicates = [HasADX], Constraints = "$src1 = $dst" in {
1207-
let SchedRW = [WriteADC], isCommutable = 1 in {
1208-
def ADCX32rr : ADCOXOpRR<0xF6, "adcx", Xi32>, T8PD;
1209-
def ADCX64rr : ADCOXOpRR<0xF6, "adcx", Xi64>, T8PD;
1210-
1211-
def ADOX32rr : ADCOXOpRR<0xF6, "adox", Xi32>, T8XS;
1212-
def ADOX64rr : ADCOXOpRR<0xF6, "adox", Xi64>, T8XS;
1205+
let SchedRW = [WriteADC] in {
1206+
def ADCX32rr : ADCOXOpRR<"adcx", Xi32>, T8PD;
1207+
def ADCX64rr : ADCOXOpRR<"adcx", Xi64>, T8PD;
1208+
def ADOX32rr : ADCOXOpRR<"adox", Xi32>, T8XS;
1209+
def ADOX64rr : ADCOXOpRR<"adox", Xi64>, T8XS;
12131210
}
12141211

12151212
let SchedRW = [WriteADC.Folded, WriteADC.ReadAfterFold,
12161213
// Memory operand.
12171214
ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault,
12181215
// Implicit read of EFLAGS
12191216
WriteADC.ReadAfterFold] in {
1220-
def ADCX32rm : ADCOXOpRM<0xF6, "adcx", Xi32>, T8PD;
1221-
def ADCX64rm : ADCOXOpRM<0xF6, "adcx", Xi64>, T8PD;
1222-
1223-
def ADOX32rm : ADCOXOpRM<0xF6, "adox", Xi32>, T8XS;
1224-
def ADOX64rm : ADCOXOpRM<0xF6, "adox", Xi64>, T8XS;
1217+
def ADCX32rm : ADCOXOpRM<"adcx", Xi32>, T8PD;
1218+
def ADCX64rm : ADCOXOpRM<"adcx", Xi64>, T8PD;
1219+
def ADOX32rm : ADCOXOpRM<"adox", Xi32>, T8XS;
1220+
def ADOX64rm : ADCOXOpRM<"adox", Xi64>, T8XS;
12251221
}
12261222
}

‎llvm/lib/Target/X86/X86InstrUtils.td

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,7 @@ class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
147147
Operand immoperand, SDPatternOperator immoperator,
148148
SDPatternOperator immnosuoperator, Operand imm8operand,
149149
SDPatternOperator imm8operator, SDPatternOperator imm8nosuoperator,
150-
bit hasOddOpcode, OperandSize opSize,
150+
bit hasEvenOpcode, OperandSize opSize,
151151
bit hasREX_W> {
152152
/// VT - This is the value type itself.
153153
ValueType VT = vt;
@@ -197,10 +197,10 @@ class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
197197

198198
SDPatternOperator Imm8NoSuOperator = imm8nosuoperator;
199199

200-
/// HasOddOpcode - This bit is true if the instruction should have an odd (as
201-
/// opposed to even) opcode. Operations on i8 are usually even, operations on
202-
/// other datatypes are odd.
203-
bit HasOddOpcode = hasOddOpcode;
200+
/// HasEvenOpcode - This bit is true if the instruction should have an even (as
201+
/// opposed to odd) opcode. Operations on i8 are even, operations on
202+
/// other datatypes are usually odd.
203+
bit HasEvenOpcode = hasEvenOpcode;
204204

205205
/// OpSize - Selects whether the instruction needs a 0x66 prefix based on
206206
/// 16-bit vs 32-bit mode. i8/i64 set this to OpSizeFixed. i16 sets this
@@ -216,16 +216,16 @@ def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">;
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def Xi8 : X86TypeInfo<i8, "b", GR8, loadi8, i8mem, Imm8, i8imm,
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imm_su, imm, i8imm, invalid_node, invalid_node,
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0, OpSizeFixed, 0>;
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1, OpSizeFixed, 0>;
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def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem, Imm16, i16imm,
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imm_su, imm, i16i8imm, i16immSExt8_su, i16immSExt8,
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1, OpSize16, 0>;
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0, OpSize16, 0>;
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def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem, Imm32, i32imm,
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imm_su, imm, i32i8imm, i32immSExt8_su, i32immSExt8,
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1, OpSize32, 0>;
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0, OpSize32, 0>;
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def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem, Imm32S, i64i32imm,
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i64immSExt32_su, i64immSExt32, i64i8imm, i64immSExt8_su,
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i64immSExt8, 1, OpSizeFixed, 1>;
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i64immSExt8, 0, OpSizeFixed, 1>;
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// Group template arguments that can be derived from the vector type (EltNum x
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// EltVT). These are things like the register class for the writemask, etc.
@@ -992,8 +992,8 @@ class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
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string mnemonic, string args, list<dag> pattern>
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: I<{opcode{7}, opcode{6}, opcode{5}, opcode{4},
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opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode },
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f, outs, ins,
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opcode{3}, opcode{2}, opcode{1},
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!if(!eq(typeinfo.HasEvenOpcode, 1), 0, opcode{0})}, f, outs, ins,
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!strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern> {
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let hasSideEffects = 0;

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