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Thorsten Schütt
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[GlobalISel][AArch64] Legalize G_UADDSAT, G_SADDSAT, G_USUBSAT, and G… (#114664)
…_SSUBSAT sve-int-imm.ll also tests saturation, but it has unsupported splats.
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‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

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@@ -1280,6 +1280,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
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getActionDefinitionsBuilder({G_UADDSAT, G_SADDSAT, G_USUBSAT, G_SSUBSAT})
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.legalFor({v2s64, v2s32, v4s32, v4s16, v8s16, v8s8, v16s8})
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.legalFor(HasSVE, {nxv2s64, nxv4s32, nxv8s16, nxv16s8})
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.clampNumElements(0, v8s8, v16s8)
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.clampNumElements(0, v4s16, v8s16)
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.clampNumElements(0, v2s32, v4s32)

‎llvm/test/CodeGen/AArch64/sve-saturating-arith.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=aarch64 -mattr=+sve -verify-machineinstrs %s -o - | FileCheck %s
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; RUN: llc -mtriple=aarch64 -mattr=+sve -aarch64-enable-gisel-sve=1 -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
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; SQADD
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define <vscale x 16 x i8> @sqadd_i8_low(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: sqadd_i8_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sqadd z0.b, z0.b, z1.b
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @sqadd_i16_low(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: sqadd_i16_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sqadd z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @sqadd_i32_low(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: sqadd_i32_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sqadd z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @sqadd_i64_low(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: sqadd_i64_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sqadd z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %res
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}
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; UQADD
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define <vscale x 16 x i8> @uqadd_i8_low(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: uqadd_i8_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uqadd z0.b, z0.b, z1.b
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @uqadd_i16_low(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: uqadd_i16_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uqadd z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @uqadd_i32_low(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: uqadd_i32_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uqadd z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @uqadd_i64_low(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: uqadd_i64_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uqadd z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %res
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}
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; SQSUB
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define <vscale x 16 x i8> @sqsub_i8_low(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: sqsub_i8_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sqsub z0.b, z0.b, z1.b
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @sqsub_i16_low(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: sqsub_i16_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sqsub z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @sqsub_i32_low(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: sqsub_i32_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sqsub z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @sqsub_i64_low(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: sqsub_i64_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sqsub z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %res
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}
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; UQSUB
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define <vscale x 16 x i8> @uqsub_i8_low(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: uqsub_i8_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uqsub z0.b, z0.b, z1.b
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 8 x i16> @uqsub_i16_low(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: uqsub_i16_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uqsub z0.h, z0.h, z1.h
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @uqsub_i32_low(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: uqsub_i32_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uqsub z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @uqsub_i64_low(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: uqsub_i64_low:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uqsub z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
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ret <vscale x 2 x i64> %res
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}
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declare <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
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declare <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)

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