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RegisterCoalescer: Fix implicit operand handling during rematerialize (#75271)
If the rematerialize was placing a subregister into a super register, and implicit operands referenced the original register, we need to add undef flags to the now-subregister indexed implicit operands. Depends #75152
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‎llvm/lib/CodeGen/RegisterCoalescer.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1611,8 +1611,7 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
16111611
LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
16121612
}
16131613

1614-
if (NewMI.getOperand(0).getSubReg())
1615-
NewMI.getOperand(0).setIsUndef();
1614+
NewMI.setRegisterDefReadUndef(NewMI.getOperand(0).getReg());
16161615

16171616
// Transfer over implicit operands to the rematerialized instruction.
16181617
for (MachineOperand &MO : ImplicitOps)

‎llvm/test/CodeGen/X86/coalescer-dead-flag-verifier-error.ll

Lines changed: 131 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,131 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc -mtriple=x86_64-pc-linux-gnu -verify-coalescing < %s | FileCheck %s
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4+
%"class.llvm::APInt." = type <{ %union.anon., i32, [4 x i8] }>
5+
%union.anon. = type { i64 }
6+
7+
define void @_ZNK4llvm5APInt21multiplicativeInverseERKS0_(ptr %r) {
8+
; CHECK-LABEL: _ZNK4llvm5APInt21multiplicativeInverseERKS0_:
9+
; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xorl %eax, %eax
11+
; CHECK-NEXT: xorl %edx, %edx
12+
; CHECK-NEXT: xorl %ecx, %ecx
13+
; CHECK-NEXT: jmp .LBB0_1
14+
; CHECK-NEXT: .p2align 4, 0x90
15+
; CHECK-NEXT: .LBB0_4: # %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i
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; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: movl %edx, %edx
18+
; CHECK-NEXT: shlq $4, %rdx
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; CHECK-NEXT: movl $0, (%rdi,%rdx)
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; CHECK-NEXT: movl %ecx, %edx
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; CHECK-NEXT: .LBB0_1: # %bb
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; CHECK-NEXT: # =>This Loop Header: Depth=1
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; CHECK-NEXT: # Child Loop BB0_3 Depth 2
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; CHECK-NEXT: xorl $1, %ecx
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; CHECK-NEXT: xorl %esi, %esi
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; CHECK-NEXT: movq %rcx, %r8
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB0_4
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB0_3: # %for.body.i.i.i.i.i.3
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; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
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; CHECK-NEXT: # => This Inner Loop Header: Depth=2
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; CHECK-NEXT: orq $1, %r8
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; CHECK-NEXT: orq $1, %rsi
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: je .LBB0_3
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; CHECK-NEXT: jmp .LBB0_4
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entry:
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br label %bb
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bb: ; preds = %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i, %entry
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%i.0 = phi i32 [ 0, %entry ], [ %xor, %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i ]
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%xor = xor i32 %i.0, 1
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%idxprom = zext nneg i32 %xor to i64
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br label %for.body.i.i.i.i.i
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for.body.i.i.i.i.i: ; preds = %for.body.i.i.i.i.i.3, %bb
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%lsr.iv37 = phi i64 [ %lsr.iv.next38, %for.body.i.i.i.i.i.3 ], [ 0, %bb ]
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%lsr.iv = phi i64 [ %lsr.iv.next, %for.body.i.i.i.i.i.3 ], [ %idxprom, %bb ]
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%exitcond.not.i.i.i.i.i.2 = icmp eq i64 0, 1
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br i1 %exitcond.not.i.i.i.i.i.2, label %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i, label %for.body.i.i.i.i.i.3
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for.body.i.i.i.i.i.3: ; preds = %for.body.i.i.i.i.i
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%sunkaddr55 = mul i64 %lsr.iv37, 0
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%i = xor i64 %lsr.iv, 0
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%lsr.iv.next = or i64 %lsr.iv, 1
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%lsr.iv.next38 = or i64 %lsr.iv37, 1
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br label %for.body.i.i.i.i.i
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_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i: ; preds = %for.body.i.i.i.i.i
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%idxprom12 = zext nneg i32 %i.0 to i64
62+
%arrayidx13 = getelementptr [2 x %"class.llvm::APInt."], ptr %r, i64 0, i64 %idxprom12
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store i32 0, ptr %arrayidx13, align 4
64+
br label %bb
65+
}
66+
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; This variant hit an assert and never reached the verifier error
68+
define void @_ZNK4llvm5APInt21multiplicativeInverseERKS0__assert(ptr %r) {
69+
; CHECK-LABEL: _ZNK4llvm5APInt21multiplicativeInverseERKS0__assert:
70+
; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: xorl %ecx, %ecx
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; CHECK-NEXT: jmp .LBB1_1
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB1_4: # %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i
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; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1
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; CHECK-NEXT: movl %edx, %edx
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; CHECK-NEXT: shlq $4, %rdx
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; CHECK-NEXT: movl $0, (%rdi,%rdx)
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; CHECK-NEXT: movl %ecx, %edx
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; CHECK-NEXT: .LBB1_1: # %bb
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; CHECK-NEXT: # =>This Loop Header: Depth=1
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; CHECK-NEXT: # Child Loop BB1_3 Depth 2
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; CHECK-NEXT: xorl $1, %ecx
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; CHECK-NEXT: movq %rcx, %rsi
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; CHECK-NEXT: shlq $4, %rsi
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; CHECK-NEXT: movq (%rsi), %rsi
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; CHECK-NEXT: xorl %r8d, %r8d
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB1_4
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB1_3: # %for.body.i.i.i.i.i.3
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; CHECK-NEXT: # Parent Loop BB1_1 Depth=1
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; CHECK-NEXT: # => This Inner Loop Header: Depth=2
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; CHECK-NEXT: orq $1, %rsi
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; CHECK-NEXT: orq $1, %r8
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: je .LBB1_3
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; CHECK-NEXT: jmp .LBB1_4
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entry:
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br label %bb
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bb: ; preds = %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i, %entry
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%i.0 = phi i32 [ 0, %entry ], [ %xor, %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i ]
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%xor = xor i32 %i.0, 1
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%idxprom = zext nneg i32 %xor to i64
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%arrayidx = getelementptr [2 x %"class.llvm::APInt."], ptr null, i64 0, i64 %idxprom
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%i.i.i.i.i.i = load ptr, ptr %arrayidx, align 16
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%i.i.i.i.i.i36 = ptrtoint ptr %i.i.i.i.i.i to i64
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br label %for.body.i.i.i.i.i
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for.body.i.i.i.i.i: ; preds = %for.body.i.i.i.i.i.3, %bb
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%lsr.iv37 = phi i64 [ %lsr.iv.next38, %for.body.i.i.i.i.i.3 ], [ 0, %bb ]
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%lsr.iv = phi i64 [ %lsr.iv.next, %for.body.i.i.i.i.i.3 ], [ %i.i.i.i.i.i36, %bb ]
116+
%exitcond.not.i.i.i.i.i.2 = icmp eq i64 0, 1
117+
br i1 %exitcond.not.i.i.i.i.i.2, label %_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i, label %for.body.i.i.i.i.i.3
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for.body.i.i.i.i.i.3: ; preds = %for.body.i.i.i.i.i
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%sunkaddr55 = mul i64 %lsr.iv37, 0
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%i = xor i64 %lsr.iv, 0
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%lsr.iv.next = or i64 %lsr.iv, 1
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%lsr.iv.next38 = or i64 %lsr.iv37, 1
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br label %for.body.i.i.i.i.i
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_ZNK4llvm5APInt13getActiveBitsEv.exit.i.i: ; preds = %for.body.i.i.i.i.i
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%idxprom12 = zext nneg i32 %i.0 to i64
128+
%arrayidx13 = getelementptr [2 x %"class.llvm::APInt."], ptr %r, i64 0, i64 %idxprom12
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store i32 0, ptr %arrayidx13, align 4
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br label %bb
131+
}

‎llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir

Lines changed: 123 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,123 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2+
# RUN: llc -mtriple=x86_64-pc-linux-gnu -verify-coalescing -run-pass=register-coalescer -o - %s | FileCheck %s
3+
4+
# The %1 = MOV32r0 is rematerialized as a subregister of %2. The
5+
# implicit-def %1 operand needs to have an undef added, just like the
6+
# main result operand.
7+
8+
---
9+
name: remat_into_subregister_set_undef_implicit_operand_subregisters
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tracksRegLiveness: true
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body: |
12+
; CHECK-LABEL: name: remat_into_subregister_set_undef_implicit_operand_subregisters
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $rdi
16+
; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_]]
18+
; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_1]]
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; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_2]].sub_32bit, implicit-def [[MOV32r0_2]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = XOR32ri [[MOV32r0_2]].sub_32bit, 1, implicit-def dead $eflags
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: JCC_1 %bb.4, 5, implicit killed undef $eflags
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[MOV32r0_1]]
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; CHECK-NEXT: dead [[SHL64ri:%[0-9]+]]:gr64_nosp = SHL64ri [[MOV32r0_]], 4, implicit-def dead $eflags
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; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = COPY [[MOV32r0_2]].sub_32bit
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; CHECK-NEXT: JMP_1 %bb.1
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bb.0:
43+
liveins: $rdi
44+
45+
undef %0.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def %0
46+
%1:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def %1
47+
undef %2.sub_32bit:gr64_with_sub_8bit = COPY %1, implicit-def %2
48+
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bb.1:
50+
%2.sub_32bit:gr64_with_sub_8bit = XOR32ri %2.sub_32bit, 1, implicit-def dead $eflags
51+
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bb.2:
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JCC_1 %bb.4, 5, implicit killed undef $eflags
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55+
bb.3:
56+
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bb.4:
58+
dead %3:gr32 = MOV32rr %1
59+
dead %4:gr64_nosp = SHL64ri %0, 4, implicit-def dead $eflags
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%1:gr32 = COPY %2.sub_32bit
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JMP_1 %bb.1
62+
63+
...
64+
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# Same, except the implicit-def on the original instruction already
66+
# has a subregister index.
67+
68+
---
69+
name: remat_into_subregister_set_undef_implicit_operand_subregisters_with_subreg
70+
tracksRegLiveness: true
71+
body: |
72+
; CHECK-LABEL: name: remat_into_subregister_set_undef_implicit_operand_subregisters_with_subreg
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; CHECK: bb.0:
74+
; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $rdi
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: undef [[MOV32r0_:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def [[MOV32r0_]]
78+
; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_1]].sub_8bit
79+
; CHECK-NEXT: undef [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def undef [[MOV32r0_2]].sub_8bit, implicit-def [[MOV32r0_2]]
80+
; CHECK-NEXT: {{ $}}
81+
; CHECK-NEXT: bb.1:
82+
; CHECK-NEXT: successors: %bb.2(0x80000000)
83+
; CHECK-NEXT: {{ $}}
84+
; CHECK-NEXT: [[MOV32r0_2:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = XOR32ri [[MOV32r0_2]].sub_32bit, 1, implicit-def dead $eflags
85+
; CHECK-NEXT: {{ $}}
86+
; CHECK-NEXT: bb.2:
87+
; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)
88+
; CHECK-NEXT: {{ $}}
89+
; CHECK-NEXT: JCC_1 %bb.4, 5, implicit killed undef $eflags
90+
; CHECK-NEXT: {{ $}}
91+
; CHECK-NEXT: bb.3:
92+
; CHECK-NEXT: successors: %bb.4(0x80000000)
93+
; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: {{ $}}
95+
; CHECK-NEXT: bb.4:
96+
; CHECK-NEXT: successors: %bb.1(0x80000000)
97+
; CHECK-NEXT: {{ $}}
98+
; CHECK-NEXT: dead [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[MOV32r0_1]]
99+
; CHECK-NEXT: dead [[SHL64ri:%[0-9]+]]:gr64_nosp = SHL64ri [[MOV32r0_]], 4, implicit-def dead $eflags
100+
; CHECK-NEXT: [[MOV32r0_1:%[0-9]+]]:gr32 = COPY [[MOV32r0_2]].sub_32bit
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; CHECK-NEXT: JMP_1 %bb.1
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bb.0:
103+
liveins: $rdi
104+
105+
undef %0.sub_32bit:gr64_with_sub_8bit = MOV32r0 implicit-def dead $eflags, implicit-def %0
106+
%1:gr32 = MOV32r0 implicit-def dead $eflags, undef implicit-def %1.sub_8bit
107+
undef %2.sub_32bit:gr64_with_sub_8bit = COPY %1, implicit-def %2
108+
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bb.1:
110+
%2.sub_32bit:gr64_with_sub_8bit = XOR32ri %2.sub_32bit, 1, implicit-def dead $eflags
111+
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bb.2:
113+
JCC_1 %bb.4, 5, implicit killed undef $eflags
114+
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bb.3:
116+
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bb.4:
118+
dead %3:gr32 = MOV32rr %1
119+
dead %4:gr64_nosp = SHL64ri %0, 4, implicit-def dead $eflags
120+
%1:gr32 = COPY %2.sub_32bit
121+
JMP_1 %bb.1
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...

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