fixup! [RISCV] Add CFI information for vector callee-saved registers

Author: 4vtomat

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

@@ -695,6 +695,7 @@ define void @insert_v2i64_nxv16i64_hi(ptr %psv, ptr %out) {
 ; RV32VLA-NEXT:    vs8r.v v8, (a0)
 ; RV32VLA-NEXT:    vs8r.v v16, (a1)
 ; RV32VLA-NEXT:    addi sp, s0, -80
+; RV32VLA-NEXT:    .cfi_def_cfa sp, 80
 ; RV32VLA-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
 ; RV32VLA-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
 ; RV32VLA-NEXT:    addi sp, sp, 80
@@ -728,6 +729,7 @@ define void @insert_v2i64_nxv16i64_hi(ptr %psv, ptr %out) {
 ; RV64VLA-NEXT:    vs8r.v v8, (a0)
 ; RV64VLA-NEXT:    vs8r.v v16, (a1)
 ; RV64VLA-NEXT:    addi sp, s0, -80
+; RV64VLA-NEXT:    .cfi_def_cfa sp, 80
 ; RV64VLA-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
 ; RV64VLA-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
 ; RV64VLA-NEXT:    addi sp, sp, 80
@@ -756,6 +758,7 @@ define void @insert_v2i64_nxv16i64_hi(ptr %psv, ptr %out) {
 ; RV32VLS-NEXT:    vs8r.v v8, (a0)
 ; RV32VLS-NEXT:    vs8r.v v16, (a1)
 ; RV32VLS-NEXT:    addi sp, s0, -80
+; RV32VLS-NEXT:    .cfi_def_cfa sp, 80
 ; RV32VLS-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
 ; RV32VLS-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
 ; RV32VLS-NEXT:    addi sp, sp, 80
@@ -784,6 +787,7 @@ define void @insert_v2i64_nxv16i64_hi(ptr %psv, ptr %out) {
 ; RV64VLS-NEXT:    vs8r.v v8, (a0)
 ; RV64VLS-NEXT:    vs8r.v v16, (a1)
 ; RV64VLS-NEXT:    addi sp, s0, -80
+; RV64VLS-NEXT:    .cfi_def_cfa sp, 80
 ; RV64VLS-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
 ; RV64VLS-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
 ; RV64VLS-NEXT:    addi sp, sp, 80

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-concat.ll

@@ -257,6 +257,7 @@ define <32 x i32> @concat_8xv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x
 ; VLA-NEXT:    csrr a0, vlenb
 ; VLA-NEXT:    slli a0, a0, 5
 ; VLA-NEXT:    add sp, sp, a0
+; VLA-NEXT:    .cfi_def_cfa sp, 16
 ; VLA-NEXT:    addi sp, sp, 16
 ; VLA-NEXT:    ret
 ;
@@ -303,6 +304,7 @@ define <32 x i32> @concat_8xv4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x
 ; VLS-NEXT:    vl8r.v v16, (a0) # Unknown-size Folded Reload
 ; VLS-NEXT:    vslideup.vi v8, v16, 28
 ; VLS-NEXT:    addi sp, sp, 512
+; VLS-NEXT:    .cfi_def_cfa sp, 16
 ; VLS-NEXT:    addi sp, sp, 16
 ; VLS-NEXT:    ret
   %ab = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>