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[RISCV] Support bf16 vmv.v.v and vmerge.vvm intrinsics with zvfbfmin (#101611)
These two intrinsics are supported for f16 with `zvfhmin`, also support them in bf16 to make it aligned to f16. This resolve: riscv-non-isa/rvv-intrinsic-doc#349
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10 files changed

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‎clang/include/clang/Basic/riscv_vector.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1378,6 +1378,9 @@ let HasMasked = false,
13781378
let RequiredFeatures = ["Zvfhmin"] in
13791379
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "x",
13801380
[["v", "v", "vv"]]>;
1381+
let RequiredFeatures = ["Zvfbfmin"] in
1382+
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "y",
1383+
[["v", "v", "vv"]]>;
13811384
let SupportOverloading = false in
13821385
defm vmv_v : RVVOutBuiltinSet<"vmv_v_x", "csil",
13831386
[["x", "v", "ve"],
@@ -1890,6 +1893,9 @@ let HasMasked = false,
18901893
let RequiredFeatures = ["Zvfhmin"] in
18911894
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "x",
18921895
[["vvm", "v", "vvvm"]]>;
1896+
let RequiredFeatures = ["Zvfbfmin"] in
1897+
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "y",
1898+
[["vvm", "v", "vvvm"]]>;
18931899
defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd",
18941900
[["vfm", "v", "vvem"]]>;
18951901
}

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmerge.c

Lines changed: 60 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

@@ -1037,3 +1037,62 @@ vfloat64m8_t test_vmerge_vvm_f64m8(vfloat64m8_t op1, vfloat64m8_t op2, vbool8_t
10371037
return __riscv_vmerge_vvm_f64m8(op1, op2, mask, vl);
10381038
}
10391039

1040+
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vmerge_vvm_bf16mf4
1041+
// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[OP1:%.*]], <vscale x 1 x bfloat> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1042+
// CHECK-RV64-NEXT: entry:
1043+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vmerge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[OP1]], <vscale x 1 x bfloat> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1044+
// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
1045+
//
1046+
vbfloat16mf4_t test_vmerge_vvm_bf16mf4(vbfloat16mf4_t op1, vbfloat16mf4_t op2, vbool64_t mask, size_t vl) {
1047+
return __riscv_vmerge_vvm_bf16mf4(op1, op2, mask, vl);
1048+
}
1049+
1050+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vmerge_vvm_bf16mf2
1051+
// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[OP1:%.*]], <vscale x 2 x bfloat> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1052+
// CHECK-RV64-NEXT: entry:
1053+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vmerge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[OP1]], <vscale x 2 x bfloat> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1054+
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
1055+
//
1056+
vbfloat16mf2_t test_vmerge_vvm_bf16mf2(vbfloat16mf2_t op1, vbfloat16mf2_t op2, vbool32_t mask, size_t vl) {
1057+
return __riscv_vmerge_vvm_bf16mf2(op1, op2, mask, vl);
1058+
}
1059+
1060+
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vmerge_vvm_bf16m1
1061+
// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[OP1:%.*]], <vscale x 4 x bfloat> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1062+
// CHECK-RV64-NEXT: entry:
1063+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vmerge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[OP1]], <vscale x 4 x bfloat> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1064+
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
1065+
//
1066+
vbfloat16m1_t test_vmerge_vvm_bf16m1(vbfloat16m1_t op1, vbfloat16m1_t op2, vbool16_t mask, size_t vl) {
1067+
return __riscv_vmerge_vvm_bf16m1(op1, op2, mask, vl);
1068+
}
1069+
1070+
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vmerge_vvm_bf16m2
1071+
// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[OP1:%.*]], <vscale x 8 x bfloat> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1072+
// CHECK-RV64-NEXT: entry:
1073+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vmerge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[OP1]], <vscale x 8 x bfloat> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1074+
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
1075+
//
1076+
vbfloat16m2_t test_vmerge_vvm_bf16m2(vbfloat16m2_t op1, vbfloat16m2_t op2, vbool8_t mask, size_t vl) {
1077+
return __riscv_vmerge_vvm_bf16m2(op1, op2, mask, vl);
1078+
}
1079+
1080+
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vmerge_vvm_bf16m4
1081+
// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[OP1:%.*]], <vscale x 16 x bfloat> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1082+
// CHECK-RV64-NEXT: entry:
1083+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vmerge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[OP1]], <vscale x 16 x bfloat> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
1084+
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
1085+
//
1086+
vbfloat16m4_t test_vmerge_vvm_bf16m4(vbfloat16m4_t op1, vbfloat16m4_t op2, vbool4_t mask, size_t vl) {
1087+
return __riscv_vmerge_vvm_bf16m4(op1, op2, mask, vl);
1088+
}
1089+
1090+
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vmerge_vvm_bf16m8
1091+
// CHECK-RV64-SAME: (<vscale x 32 x bfloat> [[OP1:%.*]], <vscale x 32 x bfloat> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1092+
// CHECK-RV64-NEXT: entry:
1093+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vmerge.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[OP1]], <vscale x 32 x bfloat> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
1094+
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
1095+
//
1096+
vbfloat16m8_t test_vmerge_vvm_bf16m8(vbfloat16m8_t op1, vbfloat16m8_t op2, vbool2_t mask, size_t vl) {
1097+
return __riscv_vmerge_vvm_bf16m8(op1, op2, mask, vl);
1098+
}

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmv.c

Lines changed: 61 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

@@ -1917,3 +1917,63 @@ vuint64m8_t test_vmv_s_x_u64m8(uint64_t src, size_t vl) {
19171917
return __riscv_vmv_s_x_u64m8(src, vl);
19181918
}
19191919

1920+
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vmv_v_v_bf16mf4
1921+
// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1922+
// CHECK-RV64-NEXT: entry:
1923+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vmv.v.v.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[SRC]], i64 [[VL]])
1924+
// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
1925+
//
1926+
vbfloat16mf4_t test_vmv_v_v_bf16mf4(vbfloat16mf4_t src, size_t vl) {
1927+
return __riscv_vmv_v_v_bf16mf4(src, vl);
1928+
}
1929+
1930+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vmv_v_v_bf16mf2
1931+
// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1932+
// CHECK-RV64-NEXT: entry:
1933+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vmv.v.v.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[SRC]], i64 [[VL]])
1934+
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
1935+
//
1936+
vbfloat16mf2_t test_vmv_v_v_bf16mf2(vbfloat16mf2_t src, size_t vl) {
1937+
return __riscv_vmv_v_v_bf16mf2(src, vl);
1938+
}
1939+
1940+
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vmv_v_v_bf16m1
1941+
// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1942+
// CHECK-RV64-NEXT: entry:
1943+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vmv.v.v.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[SRC]], i64 [[VL]])
1944+
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
1945+
//
1946+
vbfloat16m1_t test_vmv_v_v_bf16m1(vbfloat16m1_t src, size_t vl) {
1947+
return __riscv_vmv_v_v_bf16m1(src, vl);
1948+
}
1949+
1950+
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vmv_v_v_bf16m2
1951+
// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1952+
// CHECK-RV64-NEXT: entry:
1953+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vmv.v.v.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[SRC]], i64 [[VL]])
1954+
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
1955+
//
1956+
vbfloat16m2_t test_vmv_v_v_bf16m2(vbfloat16m2_t src, size_t vl) {
1957+
return __riscv_vmv_v_v_bf16m2(src, vl);
1958+
}
1959+
1960+
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vmv_v_v_bf16m4
1961+
// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1962+
// CHECK-RV64-NEXT: entry:
1963+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vmv.v.v.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[SRC]], i64 [[VL]])
1964+
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
1965+
//
1966+
vbfloat16m4_t test_vmv_v_v_bf16m4(vbfloat16m4_t src, size_t vl) {
1967+
return __riscv_vmv_v_v_bf16m4(src, vl);
1968+
}
1969+
1970+
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vmv_v_v_bf16m8
1971+
// CHECK-RV64-SAME: (<vscale x 32 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1972+
// CHECK-RV64-NEXT: entry:
1973+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vmv.v.v.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[SRC]], i64 [[VL]])
1974+
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
1975+
//
1976+
vbfloat16m8_t test_vmv_v_v_bf16m8(vbfloat16m8_t src, size_t vl) {
1977+
return __riscv_vmv_v_v_bf16m8(src, vl);
1978+
}
1979+

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmerge.c

Lines changed: 61 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

@@ -1037,3 +1037,63 @@ vfloat64m8_t test_vmerge_vvm_f64m8(vfloat64m8_t op1, vfloat64m8_t op2, vbool8_t
10371037
return __riscv_vmerge(op1, op2, mask, vl);
10381038
}
10391039

1040+
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vmerge_vvm_bf16mf4
1041+
// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[OP1:%.*]], <vscale x 1 x bfloat> [[OP2:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1042+
// CHECK-RV64-NEXT: entry:
1043+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vmerge.nxv1bf16.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[OP1]], <vscale x 1 x bfloat> [[OP2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]])
1044+
// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
1045+
//
1046+
vbfloat16mf4_t test_vmerge_vvm_bf16mf4(vbfloat16mf4_t op1, vbfloat16mf4_t op2, vbool64_t mask, size_t vl) {
1047+
return __riscv_vmerge(op1, op2, mask, vl);
1048+
}
1049+
1050+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vmerge_vvm_bf16mf2
1051+
// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[OP1:%.*]], <vscale x 2 x bfloat> [[OP2:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1052+
// CHECK-RV64-NEXT: entry:
1053+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vmerge.nxv2bf16.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[OP1]], <vscale x 2 x bfloat> [[OP2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]])
1054+
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
1055+
//
1056+
vbfloat16mf2_t test_vmerge_vvm_bf16mf2(vbfloat16mf2_t op1, vbfloat16mf2_t op2, vbool32_t mask, size_t vl) {
1057+
return __riscv_vmerge(op1, op2, mask, vl);
1058+
}
1059+
1060+
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vmerge_vvm_bf16m1
1061+
// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[OP1:%.*]], <vscale x 4 x bfloat> [[OP2:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1062+
// CHECK-RV64-NEXT: entry:
1063+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vmerge.nxv4bf16.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[OP1]], <vscale x 4 x bfloat> [[OP2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]])
1064+
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
1065+
//
1066+
vbfloat16m1_t test_vmerge_vvm_bf16m1(vbfloat16m1_t op1, vbfloat16m1_t op2, vbool16_t mask, size_t vl) {
1067+
return __riscv_vmerge(op1, op2, mask, vl);
1068+
}
1069+
1070+
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vmerge_vvm_bf16m2
1071+
// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[OP1:%.*]], <vscale x 8 x bfloat> [[OP2:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1072+
// CHECK-RV64-NEXT: entry:
1073+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vmerge.nxv8bf16.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[OP1]], <vscale x 8 x bfloat> [[OP2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]])
1074+
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
1075+
//
1076+
vbfloat16m2_t test_vmerge_vvm_bf16m2(vbfloat16m2_t op1, vbfloat16m2_t op2, vbool8_t mask, size_t vl) {
1077+
return __riscv_vmerge(op1, op2, mask, vl);
1078+
}
1079+
1080+
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vmerge_vvm_bf16m4
1081+
// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[OP1:%.*]], <vscale x 16 x bfloat> [[OP2:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1082+
// CHECK-RV64-NEXT: entry:
1083+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vmerge.nxv16bf16.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[OP1]], <vscale x 16 x bfloat> [[OP2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]])
1084+
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
1085+
//
1086+
vbfloat16m4_t test_vmerge_vvm_bf16m4(vbfloat16m4_t op1, vbfloat16m4_t op2, vbool4_t mask, size_t vl) {
1087+
return __riscv_vmerge(op1, op2, mask, vl);
1088+
}
1089+
1090+
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vmerge_vvm_bf16m8
1091+
// CHECK-RV64-SAME: (<vscale x 32 x bfloat> [[OP1:%.*]], <vscale x 32 x bfloat> [[OP2:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1092+
// CHECK-RV64-NEXT: entry:
1093+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vmerge.nxv32bf16.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[OP1]], <vscale x 32 x bfloat> [[OP2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]])
1094+
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
1095+
//
1096+
vbfloat16m8_t test_vmerge_vvm_bf16m8(vbfloat16m8_t op1, vbfloat16m8_t op2, vbool2_t mask, size_t vl) {
1097+
return __riscv_vmerge(op1, op2, mask, vl);
1098+
}
1099+

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmv.c

Lines changed: 61 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
4-
// RUN: -target-feature +zvfhmin -disable-O0-optnone \
4+
// RUN: -target-feature +zvfhmin -target-feature +zvfbfmin -disable-O0-optnone \
55
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
66
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
77

@@ -1037,3 +1037,63 @@ uint64_t test_vmv_x_s_u64m8_u64(vuint64m8_t src) {
10371037
return __riscv_vmv_x(src);
10381038
}
10391039

1040+
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x bfloat> @test_vmv_v_v_bf16mf4
1041+
// CHECK-RV64-SAME: (<vscale x 1 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1042+
// CHECK-RV64-NEXT: entry:
1043+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x bfloat> @llvm.riscv.vmv.v.v.nxv1bf16.i64(<vscale x 1 x bfloat> poison, <vscale x 1 x bfloat> [[SRC]], i64 [[VL]])
1044+
// CHECK-RV64-NEXT: ret <vscale x 1 x bfloat> [[TMP0]]
1045+
//
1046+
vbfloat16mf4_t test_vmv_v_v_bf16mf4(vbfloat16mf4_t src, size_t vl) {
1047+
return __riscv_vmv_v(src, vl);
1048+
}
1049+
1050+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x bfloat> @test_vmv_v_v_bf16mf2
1051+
// CHECK-RV64-SAME: (<vscale x 2 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1052+
// CHECK-RV64-NEXT: entry:
1053+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x bfloat> @llvm.riscv.vmv.v.v.nxv2bf16.i64(<vscale x 2 x bfloat> poison, <vscale x 2 x bfloat> [[SRC]], i64 [[VL]])
1054+
// CHECK-RV64-NEXT: ret <vscale x 2 x bfloat> [[TMP0]]
1055+
//
1056+
vbfloat16mf2_t test_vmv_v_v_bf16mf2(vbfloat16mf2_t src, size_t vl) {
1057+
return __riscv_vmv_v(src, vl);
1058+
}
1059+
1060+
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x bfloat> @test_vmv_v_v_bf16m1
1061+
// CHECK-RV64-SAME: (<vscale x 4 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1062+
// CHECK-RV64-NEXT: entry:
1063+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x bfloat> @llvm.riscv.vmv.v.v.nxv4bf16.i64(<vscale x 4 x bfloat> poison, <vscale x 4 x bfloat> [[SRC]], i64 [[VL]])
1064+
// CHECK-RV64-NEXT: ret <vscale x 4 x bfloat> [[TMP0]]
1065+
//
1066+
vbfloat16m1_t test_vmv_v_v_bf16m1(vbfloat16m1_t src, size_t vl) {
1067+
return __riscv_vmv_v(src, vl);
1068+
}
1069+
1070+
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x bfloat> @test_vmv_v_v_bf16m2
1071+
// CHECK-RV64-SAME: (<vscale x 8 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1072+
// CHECK-RV64-NEXT: entry:
1073+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x bfloat> @llvm.riscv.vmv.v.v.nxv8bf16.i64(<vscale x 8 x bfloat> poison, <vscale x 8 x bfloat> [[SRC]], i64 [[VL]])
1074+
// CHECK-RV64-NEXT: ret <vscale x 8 x bfloat> [[TMP0]]
1075+
//
1076+
vbfloat16m2_t test_vmv_v_v_bf16m2(vbfloat16m2_t src, size_t vl) {
1077+
return __riscv_vmv_v(src, vl);
1078+
}
1079+
1080+
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x bfloat> @test_vmv_v_v_bf16m4
1081+
// CHECK-RV64-SAME: (<vscale x 16 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1082+
// CHECK-RV64-NEXT: entry:
1083+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x bfloat> @llvm.riscv.vmv.v.v.nxv16bf16.i64(<vscale x 16 x bfloat> poison, <vscale x 16 x bfloat> [[SRC]], i64 [[VL]])
1084+
// CHECK-RV64-NEXT: ret <vscale x 16 x bfloat> [[TMP0]]
1085+
//
1086+
vbfloat16m4_t test_vmv_v_v_bf16m4(vbfloat16m4_t src, size_t vl) {
1087+
return __riscv_vmv_v(src, vl);
1088+
}
1089+
1090+
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x bfloat> @test_vmv_v_v_bf16m8
1091+
// CHECK-RV64-SAME: (<vscale x 32 x bfloat> [[SRC:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
1092+
// CHECK-RV64-NEXT: entry:
1093+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x bfloat> @llvm.riscv.vmv.v.v.nxv32bf16.i64(<vscale x 32 x bfloat> poison, <vscale x 32 x bfloat> [[SRC]], i64 [[VL]])
1094+
// CHECK-RV64-NEXT: ret <vscale x 32 x bfloat> [[TMP0]]
1095+
//
1096+
vbfloat16m8_t test_vmv_v_v_bf16m8(vbfloat16m8_t src, size_t vl) {
1097+
return __riscv_vmv_v(src, vl);
1098+
}
1099+

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