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SystemZ: Handle gr128 to fp128 copies in copyPhysReg
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llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

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@@ -856,6 +856,22 @@ void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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return;
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}
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if (SystemZ::FP128BitRegClass.contains(DestReg) &&
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SystemZ::GR128BitRegClass.contains(SrcReg)) {
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MCRegister DestRegHi = RI.getSubReg(DestReg, SystemZ::subreg_h64);
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MCRegister DestRegLo = RI.getSubReg(DestReg, SystemZ::subreg_l64);
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MCRegister SrcRegHi = RI.getSubReg(SrcReg, SystemZ::subreg_h64);
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MCRegister SrcRegLo = RI.getSubReg(SrcReg, SystemZ::subreg_l64);
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BuildMI(MBB, MBBI, DL, get(SystemZ::LDGR), DestRegHi)
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.addReg(SrcRegHi)
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.addReg(DestReg, RegState::ImplicitDefine);
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BuildMI(MBB, MBBI, DL, get(SystemZ::LDGR), DestRegLo)
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.addReg(SrcRegLo, getKillRegState(KillSrc));
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return;
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}
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// Move CC value from a GR32.
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if (DestReg == SystemZ::CC) {
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unsigned Opcode =
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@@ -0,0 +1,82 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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# RUN: llc -mtriple=s390x-ibm-linux -mcpu=z13 -run-pass=postrapseudos -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: copy_gr128_to_fp128__r0q_to_f0q
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0q
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; CHECK-LABEL: name: copy_gr128_to_fp128__r0q_to_f0q
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; CHECK: liveins: $r0q
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $f0d = LDGR $r0d, implicit-def $f0q
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; CHECK-NEXT: $f2d = LDGR $r1d
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; CHECK-NEXT: Return implicit $f0q
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$f0q = COPY $r0q
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Return implicit $f0q
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...
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---
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name: copy_gr128_to_fp128__r0q_to_f0q_killed
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0q
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; CHECK-LABEL: name: copy_gr128_to_fp128__r0q_to_f0q_killed
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; CHECK: liveins: $r0q
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $f0d = LDGR $r0d, implicit-def $f0q
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; CHECK-NEXT: $f2d = LDGR killed $r1d
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; CHECK-NEXT: Return implicit $f0q
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$f0q = COPY killed $r0q
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Return implicit $f0q
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...
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---
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name: copy_gr128_to_fp128__r0q_to_f0q_undef
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0q
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; CHECK-LABEL: name: copy_gr128_to_fp128__r0q_to_f0q_undef
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; CHECK: liveins: $r0q
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $f0q = KILL undef $r0q
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; CHECK-NEXT: Return implicit $f0q
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$f0q = COPY undef $r0q
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Return implicit $f0q
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...
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---
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name: copy_gr128_to_fp128__r0q_to_f0q_subreg0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0q
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; CHECK-LABEL: name: copy_gr128_to_fp128__r0q_to_f0q_subreg0
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; CHECK: liveins: $r0q
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $f0d = LDGR $r0d, implicit-def $f0q
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; CHECK-NEXT: $f2d = LDGR $r1d
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; CHECK-NEXT: Return implicit $f0q
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$f0q = COPY $r0q
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Return implicit $f0q
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...
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---
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name: copy_gr128_to_fp128__r0q_to_f0q_subreg1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r0q
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; CHECK-LABEL: name: copy_gr128_to_fp128__r0q_to_f0q_subreg1
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; CHECK: liveins: $r0q
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $f0d = LDGR $r0d, implicit-def $f0q
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; CHECK-NEXT: $f2d = LDGR $r1d
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; CHECK-NEXT: Return implicit $f0q
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$f0q = COPY $r0q
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Return implicit $f0q
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...
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