Skip to content

Commit 30b6b27

Browse files
committed
[LoongArch] Fix typos. NFC
1 parent 96e83d3 commit 30b6b27

File tree

2 files changed

+51
-51
lines changed

2 files changed

+51
-51
lines changed

llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1545,10 +1545,10 @@ foreach Inst = ["XVEXTH_Q_D", "XVEXTH_QU_DU", "XVMSKLTZ_D",
15451545
// Pat<(Intrinsic timm:$imm)
15461546
// (LAInst timm:$imm)>;
15471547
def : Pat<(int_loongarch_lasx_xvldi timm:$imm),
1548-
(XVLDI (to_valide_timm timm:$imm))>;
1548+
(XVLDI (to_valid_timm timm:$imm))>;
15491549
foreach Inst = ["XVREPLI_B", "XVREPLI_H", "XVREPLI_W", "XVREPLI_D"] in
15501550
def : Pat<(deriveLASXIntrinsic<Inst>.ret timm:$imm),
1551-
(!cast<LAInst>("Pseudo"#Inst) (to_valide_timm timm:$imm))>;
1551+
(!cast<LAInst>("Pseudo"#Inst) (to_valid_timm timm:$imm))>;
15521552

15531553
// vty: v32i8/v16i16/v8i32/v4i64
15541554
// Pat<(Intrinsic vty:$xj, timm:$imm)
@@ -1558,25 +1558,25 @@ foreach Inst = ["XVSAT_B", "XVSAT_BU", "XVNORI_B", "XVROTRI_B", "XVSLLWIL_H_B",
15581558
"XVSEQI_B", "XVSLEI_B", "XVSLEI_BU", "XVSLTI_B", "XVSLTI_BU",
15591559
"XVREPL128VEI_B", "XVBSLL_V", "XVBSRL_V", "XVSHUF4I_B"] in
15601560
def : Pat<(deriveLASXIntrinsic<Inst>.ret (v32i8 LASX256:$xj), timm:$imm),
1561-
(!cast<LAInst>(Inst) LASX256:$xj, (to_valide_timm timm:$imm))>;
1561+
(!cast<LAInst>(Inst) LASX256:$xj, (to_valid_timm timm:$imm))>;
15621562
foreach Inst = ["XVSAT_H", "XVSAT_HU", "XVROTRI_H", "XVSLLWIL_W_H",
15631563
"XVSLLWIL_WU_HU", "XVSRLRI_H", "XVSRARI_H",
15641564
"XVSEQI_H", "XVSLEI_H", "XVSLEI_HU", "XVSLTI_H", "XVSLTI_HU",
15651565
"XVREPL128VEI_H", "XVSHUF4I_H"] in
15661566
def : Pat<(deriveLASXIntrinsic<Inst>.ret (v16i16 LASX256:$xj), timm:$imm),
1567-
(!cast<LAInst>(Inst) LASX256:$xj, (to_valide_timm timm:$imm))>;
1567+
(!cast<LAInst>(Inst) LASX256:$xj, (to_valid_timm timm:$imm))>;
15681568
foreach Inst = ["XVSAT_W", "XVSAT_WU", "XVROTRI_W", "XVSLLWIL_D_W",
15691569
"XVSLLWIL_DU_WU", "XVSRLRI_W", "XVSRARI_W",
15701570
"XVSEQI_W", "XVSLEI_W", "XVSLEI_WU", "XVSLTI_W", "XVSLTI_WU",
15711571
"XVREPL128VEI_W", "XVSHUF4I_W", "XVPICKVE_W"] in
15721572
def : Pat<(deriveLASXIntrinsic<Inst>.ret (v8i32 LASX256:$xj), timm:$imm),
1573-
(!cast<LAInst>(Inst) LASX256:$xj, (to_valide_timm timm:$imm))>;
1573+
(!cast<LAInst>(Inst) LASX256:$xj, (to_valid_timm timm:$imm))>;
15741574
foreach Inst = ["XVSAT_D", "XVSAT_DU", "XVROTRI_D", "XVSRLRI_D", "XVSRARI_D",
15751575
"XVSEQI_D", "XVSLEI_D", "XVSLEI_DU", "XVSLTI_D", "XVSLTI_DU",
15761576
"XVPICKVE2GR_D", "XVPICKVE2GR_DU",
15771577
"XVREPL128VEI_D", "XVPERMI_D", "XVPICKVE_D"] in
15781578
def : Pat<(deriveLASXIntrinsic<Inst>.ret (v4i64 LASX256:$xj), timm:$imm),
1579-
(!cast<LAInst>(Inst) LASX256:$xj, (to_valide_timm timm:$imm))>;
1579+
(!cast<LAInst>(Inst) LASX256:$xj, (to_valid_timm timm:$imm))>;
15801580

15811581
// vty: v32i8/v16i16/v8i32/v4i64
15821582
// Pat<(Intrinsic vty:$xd, vty:$xj, timm:$imm)
@@ -1588,31 +1588,31 @@ foreach Inst = ["XVSRLNI_B_H", "XVSRANI_B_H", "XVSRLRNI_B_H", "XVSRARNI_B_H",
15881588
def : Pat<(deriveLASXIntrinsic<Inst>.ret
15891589
(v32i8 LASX256:$xd), (v32i8 LASX256:$xj), timm:$imm),
15901590
(!cast<LAInst>(Inst) LASX256:$xd, LASX256:$xj,
1591-
(to_valide_timm timm:$imm))>;
1591+
(to_valid_timm timm:$imm))>;
15921592
foreach Inst = ["XVSRLNI_H_W", "XVSRANI_H_W", "XVSRLRNI_H_W", "XVSRARNI_H_W",
15931593
"XVSSRLNI_H_W", "XVSSRANI_H_W", "XVSSRLNI_HU_W", "XVSSRANI_HU_W",
15941594
"XVSSRLRNI_H_W", "XVSSRARNI_H_W", "XVSSRLRNI_HU_W", "XVSSRARNI_HU_W",
15951595
"XVFRSTPI_H", "XVEXTRINS_H"] in
15961596
def : Pat<(deriveLASXIntrinsic<Inst>.ret
15971597
(v16i16 LASX256:$xd), (v16i16 LASX256:$xj), timm:$imm),
15981598
(!cast<LAInst>(Inst) LASX256:$xd, LASX256:$xj,
1599-
(to_valide_timm timm:$imm))>;
1599+
(to_valid_timm timm:$imm))>;
16001600
foreach Inst = ["XVSRLNI_W_D", "XVSRANI_W_D", "XVSRLRNI_W_D", "XVSRARNI_W_D",
16011601
"XVSSRLNI_W_D", "XVSSRANI_W_D", "XVSSRLNI_WU_D", "XVSSRANI_WU_D",
16021602
"XVSSRLRNI_W_D", "XVSSRARNI_W_D", "XVSSRLRNI_WU_D", "XVSSRARNI_WU_D",
16031603
"XVPERMI_W", "XVEXTRINS_W", "XVINSVE0_W"] in
16041604
def : Pat<(deriveLASXIntrinsic<Inst>.ret
16051605
(v8i32 LASX256:$xd), (v8i32 LASX256:$xj), timm:$imm),
16061606
(!cast<LAInst>(Inst) LASX256:$xd, LASX256:$xj,
1607-
(to_valide_timm timm:$imm))>;
1607+
(to_valid_timm timm:$imm))>;
16081608
foreach Inst = ["XVSRLNI_D_Q", "XVSRANI_D_Q", "XVSRLRNI_D_Q", "XVSRARNI_D_Q",
16091609
"XVSSRLNI_D_Q", "XVSSRANI_D_Q", "XVSSRLNI_DU_Q", "XVSSRANI_DU_Q",
16101610
"XVSSRLRNI_D_Q", "XVSSRARNI_D_Q", "XVSSRLRNI_DU_Q", "XVSSRARNI_DU_Q",
16111611
"XVSHUF4I_D", "XVEXTRINS_D", "XVINSVE0_D"] in
16121612
def : Pat<(deriveLASXIntrinsic<Inst>.ret
16131613
(v4i64 LASX256:$xd), (v4i64 LASX256:$xj), timm:$imm),
16141614
(!cast<LAInst>(Inst) LASX256:$xd, LASX256:$xj,
1615-
(to_valide_timm timm:$imm))>;
1615+
(to_valid_timm timm:$imm))>;
16161616

16171617
// vty: v32i8/v16i16/v8i32/v4i64
16181618
// Pat<(Intrinsic vty:$xd, vty:$xj, vty:$xk),
@@ -1693,42 +1693,42 @@ foreach Inst = ["XVFLOGB_D", "XVFCLASS_D", "XVFSQRT_D", "XVFRECIP_D", "XVFRSQRT_
16931693
(!cast<LAInst>(Inst) LASX256:$xj)>;
16941694

16951695
def : Pat<(int_loongarch_lasx_xvpickve_w_f v8f32:$xj, timm:$imm),
1696-
(XVPICKVE_W v8f32:$xj, (to_valide_timm timm:$imm))>;
1696+
(XVPICKVE_W v8f32:$xj, (to_valid_timm timm:$imm))>;
16971697
def : Pat<(int_loongarch_lasx_xvpickve_d_f v4f64:$xj, timm:$imm),
1698-
(XVPICKVE_D v4f64:$xj, (to_valide_timm timm:$imm))>;
1698+
(XVPICKVE_D v4f64:$xj, (to_valid_timm timm:$imm))>;
16991699

17001700
// load
17011701
def : Pat<(int_loongarch_lasx_xvld GPR:$rj, timm:$imm),
1702-
(XVLD GPR:$rj, (to_valide_timm timm:$imm))>;
1702+
(XVLD GPR:$rj, (to_valid_timm timm:$imm))>;
17031703
def : Pat<(int_loongarch_lasx_xvldx GPR:$rj, GPR:$rk),
17041704
(XVLDX GPR:$rj, GPR:$rk)>;
17051705

17061706
def : Pat<(int_loongarch_lasx_xvldrepl_b GPR:$rj, timm:$imm),
1707-
(XVLDREPL_B GPR:$rj, (to_valide_timm timm:$imm))>;
1707+
(XVLDREPL_B GPR:$rj, (to_valid_timm timm:$imm))>;
17081708
def : Pat<(int_loongarch_lasx_xvldrepl_h GPR:$rj, timm:$imm),
1709-
(XVLDREPL_H GPR:$rj, (to_valide_timm timm:$imm))>;
1709+
(XVLDREPL_H GPR:$rj, (to_valid_timm timm:$imm))>;
17101710
def : Pat<(int_loongarch_lasx_xvldrepl_w GPR:$rj, timm:$imm),
1711-
(XVLDREPL_W GPR:$rj, (to_valide_timm timm:$imm))>;
1711+
(XVLDREPL_W GPR:$rj, (to_valid_timm timm:$imm))>;
17121712
def : Pat<(int_loongarch_lasx_xvldrepl_d GPR:$rj, timm:$imm),
1713-
(XVLDREPL_D GPR:$rj, (to_valide_timm timm:$imm))>;
1713+
(XVLDREPL_D GPR:$rj, (to_valid_timm timm:$imm))>;
17141714

17151715
// store
17161716
def : Pat<(int_loongarch_lasx_xvst LASX256:$xd, GPR:$rj, timm:$imm),
1717-
(XVST LASX256:$xd, GPR:$rj, (to_valide_timm timm:$imm))>;
1717+
(XVST LASX256:$xd, GPR:$rj, (to_valid_timm timm:$imm))>;
17181718
def : Pat<(int_loongarch_lasx_xvstx LASX256:$xd, GPR:$rj, GPR:$rk),
17191719
(XVSTX LASX256:$xd, GPR:$rj, GPR:$rk)>;
17201720

17211721
def : Pat<(int_loongarch_lasx_xvstelm_b v32i8:$xd, GPR:$rj, timm:$imm, timm:$idx),
1722-
(XVSTELM_B v32i8:$xd, GPR:$rj, (to_valide_timm timm:$imm),
1723-
(to_valide_timm timm:$idx))>;
1722+
(XVSTELM_B v32i8:$xd, GPR:$rj, (to_valid_timm timm:$imm),
1723+
(to_valid_timm timm:$idx))>;
17241724
def : Pat<(int_loongarch_lasx_xvstelm_h v16i16:$xd, GPR:$rj, timm:$imm, timm:$idx),
1725-
(XVSTELM_H v16i16:$xd, GPR:$rj, (to_valide_timm timm:$imm),
1726-
(to_valide_timm timm:$idx))>;
1725+
(XVSTELM_H v16i16:$xd, GPR:$rj, (to_valid_timm timm:$imm),
1726+
(to_valid_timm timm:$idx))>;
17271727
def : Pat<(int_loongarch_lasx_xvstelm_w v8i32:$xd, GPR:$rj, timm:$imm, timm:$idx),
1728-
(XVSTELM_W v8i32:$xd, GPR:$rj, (to_valide_timm timm:$imm),
1729-
(to_valide_timm timm:$idx))>;
1728+
(XVSTELM_W v8i32:$xd, GPR:$rj, (to_valid_timm timm:$imm),
1729+
(to_valid_timm timm:$idx))>;
17301730
def : Pat<(int_loongarch_lasx_xvstelm_d v4i64:$xd, GPR:$rj, timm:$imm, timm:$idx),
1731-
(XVSTELM_D v4i64:$xd, GPR:$rj, (to_valide_timm timm:$imm),
1732-
(to_valide_timm timm:$idx))>;
1731+
(XVSTELM_D v4i64:$xd, GPR:$rj, (to_valid_timm timm:$imm),
1732+
(to_valid_timm timm:$idx))>;
17331733

17341734
} // Predicates = [HasExtLASX]

llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,7 @@ def lsxsplati32 : PatFrag<(ops node:$e0),
145145
def lsxsplati64 : PatFrag<(ops node:$e0),
146146
(v2i64 (build_vector node:$e0, node:$e0))>;
147147

148-
def to_valide_timm : SDNodeXForm<timm, [{
148+
def to_valid_timm : SDNodeXForm<timm, [{
149149
auto CN = cast<ConstantSDNode>(N);
150150
return CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(N), Subtarget->getGRLenVT());
151151
}]>;
@@ -1639,10 +1639,10 @@ foreach Inst = ["VEXTH_Q_D", "VEXTH_QU_DU", "VMSKLTZ_D",
16391639
// Pat<(Intrinsic timm:$imm)
16401640
// (LAInst timm:$imm)>;
16411641
def : Pat<(int_loongarch_lsx_vldi timm:$imm),
1642-
(VLDI (to_valide_timm timm:$imm))>;
1642+
(VLDI (to_valid_timm timm:$imm))>;
16431643
foreach Inst = ["VREPLI_B", "VREPLI_H", "VREPLI_W", "VREPLI_D"] in
16441644
def : Pat<(deriveLSXIntrinsic<Inst>.ret timm:$imm),
1645-
(!cast<LAInst>("Pseudo"#Inst) (to_valide_timm timm:$imm))>;
1645+
(!cast<LAInst>("Pseudo"#Inst) (to_valid_timm timm:$imm))>;
16461646

16471647
// vty: v16i8/v8i16/v4i32/v2i64
16481648
// Pat<(Intrinsic vty:$vj, timm:$imm)
@@ -1652,25 +1652,25 @@ foreach Inst = ["VSAT_B", "VSAT_BU", "VNORI_B", "VROTRI_B", "VSLLWIL_H_B",
16521652
"VSEQI_B", "VSLEI_B", "VSLEI_BU", "VSLTI_B", "VSLTI_BU",
16531653
"VREPLVEI_B", "VBSLL_V", "VBSRL_V", "VSHUF4I_B"] in
16541654
def : Pat<(deriveLSXIntrinsic<Inst>.ret (v16i8 LSX128:$vj), timm:$imm),
1655-
(!cast<LAInst>(Inst) LSX128:$vj, (to_valide_timm timm:$imm))>;
1655+
(!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>;
16561656
foreach Inst = ["VSAT_H", "VSAT_HU", "VROTRI_H", "VSLLWIL_W_H",
16571657
"VSLLWIL_WU_HU", "VSRLRI_H", "VSRARI_H",
16581658
"VSEQI_H", "VSLEI_H", "VSLEI_HU", "VSLTI_H", "VSLTI_HU",
16591659
"VREPLVEI_H", "VSHUF4I_H"] in
16601660
def : Pat<(deriveLSXIntrinsic<Inst>.ret (v8i16 LSX128:$vj), timm:$imm),
1661-
(!cast<LAInst>(Inst) LSX128:$vj, (to_valide_timm timm:$imm))>;
1661+
(!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>;
16621662
foreach Inst = ["VSAT_W", "VSAT_WU", "VROTRI_W", "VSLLWIL_D_W",
16631663
"VSLLWIL_DU_WU", "VSRLRI_W", "VSRARI_W",
16641664
"VSEQI_W", "VSLEI_W", "VSLEI_WU", "VSLTI_W", "VSLTI_WU",
16651665
"VREPLVEI_W", "VSHUF4I_W"] in
16661666
def : Pat<(deriveLSXIntrinsic<Inst>.ret (v4i32 LSX128:$vj), timm:$imm),
1667-
(!cast<LAInst>(Inst) LSX128:$vj, (to_valide_timm timm:$imm))>;
1667+
(!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>;
16681668
foreach Inst = ["VSAT_D", "VSAT_DU", "VROTRI_D", "VSRLRI_D", "VSRARI_D",
16691669
"VSEQI_D", "VSLEI_D", "VSLEI_DU", "VSLTI_D", "VSLTI_DU",
16701670
"VPICKVE2GR_D", "VPICKVE2GR_DU",
16711671
"VREPLVEI_D"] in
16721672
def : Pat<(deriveLSXIntrinsic<Inst>.ret (v2i64 LSX128:$vj), timm:$imm),
1673-
(!cast<LAInst>(Inst) LSX128:$vj, (to_valide_timm timm:$imm))>;
1673+
(!cast<LAInst>(Inst) LSX128:$vj, (to_valid_timm timm:$imm))>;
16741674

16751675
// vty: v16i8/v8i16/v4i32/v2i64
16761676
// Pat<(Intrinsic vty:$vd, vty:$vj, timm:$imm)
@@ -1682,31 +1682,31 @@ foreach Inst = ["VSRLNI_B_H", "VSRANI_B_H", "VSRLRNI_B_H", "VSRARNI_B_H",
16821682
def : Pat<(deriveLSXIntrinsic<Inst>.ret
16831683
(v16i8 LSX128:$vd), (v16i8 LSX128:$vj), timm:$imm),
16841684
(!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj,
1685-
(to_valide_timm timm:$imm))>;
1685+
(to_valid_timm timm:$imm))>;
16861686
foreach Inst = ["VSRLNI_H_W", "VSRANI_H_W", "VSRLRNI_H_W", "VSRARNI_H_W",
16871687
"VSSRLNI_H_W", "VSSRANI_H_W", "VSSRLNI_HU_W", "VSSRANI_HU_W",
16881688
"VSSRLRNI_H_W", "VSSRARNI_H_W", "VSSRLRNI_HU_W", "VSSRARNI_HU_W",
16891689
"VFRSTPI_H", "VEXTRINS_H"] in
16901690
def : Pat<(deriveLSXIntrinsic<Inst>.ret
16911691
(v8i16 LSX128:$vd), (v8i16 LSX128:$vj), timm:$imm),
16921692
(!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj,
1693-
(to_valide_timm timm:$imm))>;
1693+
(to_valid_timm timm:$imm))>;
16941694
foreach Inst = ["VSRLNI_W_D", "VSRANI_W_D", "VSRLRNI_W_D", "VSRARNI_W_D",
16951695
"VSSRLNI_W_D", "VSSRANI_W_D", "VSSRLNI_WU_D", "VSSRANI_WU_D",
16961696
"VSSRLRNI_W_D", "VSSRARNI_W_D", "VSSRLRNI_WU_D", "VSSRARNI_WU_D",
16971697
"VPERMI_W", "VEXTRINS_W"] in
16981698
def : Pat<(deriveLSXIntrinsic<Inst>.ret
16991699
(v4i32 LSX128:$vd), (v4i32 LSX128:$vj), timm:$imm),
17001700
(!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj,
1701-
(to_valide_timm timm:$imm))>;
1701+
(to_valid_timm timm:$imm))>;
17021702
foreach Inst = ["VSRLNI_D_Q", "VSRANI_D_Q", "VSRLRNI_D_Q", "VSRARNI_D_Q",
17031703
"VSSRLNI_D_Q", "VSSRANI_D_Q", "VSSRLNI_DU_Q", "VSSRANI_DU_Q",
17041704
"VSSRLRNI_D_Q", "VSSRARNI_D_Q", "VSSRLRNI_DU_Q", "VSSRARNI_DU_Q",
17051705
"VSHUF4I_D", "VEXTRINS_D"] in
17061706
def : Pat<(deriveLSXIntrinsic<Inst>.ret
17071707
(v2i64 LSX128:$vd), (v2i64 LSX128:$vj), timm:$imm),
17081708
(!cast<LAInst>(Inst) LSX128:$vd, LSX128:$vj,
1709-
(to_valide_timm timm:$imm))>;
1709+
(to_valid_timm timm:$imm))>;
17101710

17111711
// vty: v16i8/v8i16/v4i32/v2i64
17121712
// Pat<(Intrinsic vty:$vd, vty:$vj, vty:$vk),
@@ -1788,36 +1788,36 @@ foreach Inst = ["VFLOGB_D", "VFCLASS_D", "VFSQRT_D", "VFRECIP_D", "VFRSQRT_D",
17881788

17891789
// load
17901790
def : Pat<(int_loongarch_lsx_vld GPR:$rj, timm:$imm),
1791-
(VLD GPR:$rj, (to_valide_timm timm:$imm))>;
1791+
(VLD GPR:$rj, (to_valid_timm timm:$imm))>;
17921792
def : Pat<(int_loongarch_lsx_vldx GPR:$rj, GPR:$rk),
17931793
(VLDX GPR:$rj, GPR:$rk)>;
17941794

17951795
def : Pat<(int_loongarch_lsx_vldrepl_b GPR:$rj, timm:$imm),
1796-
(VLDREPL_B GPR:$rj, (to_valide_timm timm:$imm))>;
1796+
(VLDREPL_B GPR:$rj, (to_valid_timm timm:$imm))>;
17971797
def : Pat<(int_loongarch_lsx_vldrepl_h GPR:$rj, timm:$imm),
1798-
(VLDREPL_H GPR:$rj, (to_valide_timm timm:$imm))>;
1798+
(VLDREPL_H GPR:$rj, (to_valid_timm timm:$imm))>;
17991799
def : Pat<(int_loongarch_lsx_vldrepl_w GPR:$rj, timm:$imm),
1800-
(VLDREPL_W GPR:$rj, (to_valide_timm timm:$imm))>;
1800+
(VLDREPL_W GPR:$rj, (to_valid_timm timm:$imm))>;
18011801
def : Pat<(int_loongarch_lsx_vldrepl_d GPR:$rj, timm:$imm),
1802-
(VLDREPL_D GPR:$rj, (to_valide_timm timm:$imm))>;
1802+
(VLDREPL_D GPR:$rj, (to_valid_timm timm:$imm))>;
18031803

18041804
// store
18051805
def : Pat<(int_loongarch_lsx_vst LSX128:$vd, GPR:$rj, timm:$imm),
1806-
(VST LSX128:$vd, GPR:$rj, (to_valide_timm timm:$imm))>;
1806+
(VST LSX128:$vd, GPR:$rj, (to_valid_timm timm:$imm))>;
18071807
def : Pat<(int_loongarch_lsx_vstx LSX128:$vd, GPR:$rj, GPR:$rk),
18081808
(VSTX LSX128:$vd, GPR:$rj, GPR:$rk)>;
18091809

18101810
def : Pat<(int_loongarch_lsx_vstelm_b v16i8:$vd, GPR:$rj, timm:$imm, timm:$idx),
1811-
(VSTELM_B v16i8:$vd, GPR:$rj, (to_valide_timm timm:$imm),
1812-
(to_valide_timm timm:$idx))>;
1811+
(VSTELM_B v16i8:$vd, GPR:$rj, (to_valid_timm timm:$imm),
1812+
(to_valid_timm timm:$idx))>;
18131813
def : Pat<(int_loongarch_lsx_vstelm_h v8i16:$vd, GPR:$rj, timm:$imm, timm:$idx),
1814-
(VSTELM_H v8i16:$vd, GPR:$rj, (to_valide_timm timm:$imm),
1815-
(to_valide_timm timm:$idx))>;
1814+
(VSTELM_H v8i16:$vd, GPR:$rj, (to_valid_timm timm:$imm),
1815+
(to_valid_timm timm:$idx))>;
18161816
def : Pat<(int_loongarch_lsx_vstelm_w v4i32:$vd, GPR:$rj, timm:$imm, timm:$idx),
1817-
(VSTELM_W v4i32:$vd, GPR:$rj, (to_valide_timm timm:$imm),
1818-
(to_valide_timm timm:$idx))>;
1817+
(VSTELM_W v4i32:$vd, GPR:$rj, (to_valid_timm timm:$imm),
1818+
(to_valid_timm timm:$idx))>;
18191819
def : Pat<(int_loongarch_lsx_vstelm_d v2i64:$vd, GPR:$rj, timm:$imm, timm:$idx),
1820-
(VSTELM_D v2i64:$vd, GPR:$rj, (to_valide_timm timm:$imm),
1821-
(to_valide_timm timm:$idx))>;
1820+
(VSTELM_D v2i64:$vd, GPR:$rj, (to_valid_timm timm:$imm),
1821+
(to_valid_timm timm:$idx))>;
18221822

18231823
} // Predicates = [HasExtLSX]

0 commit comments

Comments
 (0)