@@ -1106,18 +1106,18 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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if (!isTypeLegal(VT))
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continue;
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setOperationAction({ISD::FP_ROUND, ISD::FP_EXTEND}, VT, Custom);
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- setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
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setOperationAction({ISD::STRICT_FP_ROUND, ISD::STRICT_FP_EXTEND}, VT,
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Custom);
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+ setOperationAction({ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND}, VT, Custom);
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+ setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
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+ Custom);
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+ setOperationAction(ISD::SELECT_CC, VT, Expand);
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setOperationAction({ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
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ISD::EXTRACT_SUBVECTOR},
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VT, Custom);
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- setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
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if (Subtarget.hasStdExtZfbfmin())
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setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
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- setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
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- Custom);
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- setOperationAction(ISD::SELECT_CC, VT, Expand);
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+ setOperationAction({ISD::LOAD, ISD::STORE}, VT, Custom);
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// TODO: Promote to fp32.
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}
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}
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