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[RISCV][NFC] Simplify the creation of Scheduler (#142553)
If `createMachineScheduler`/`createPostMachineScheduler` return a `nullptr`, then we will call `createSchedLive`/`createSchedPostRA` anyway. We can always create the Scheduler first and simplify the following conditions.
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llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -298,28 +298,25 @@ bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
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ScheduleDAGInstrs *
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RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
301-
ScheduleDAGMILive *DAG = nullptr;
301+
ScheduleDAGMILive *DAG = createSchedLive(C);
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if (EnableMISchedLoadStoreClustering) {
303-
DAG = createSchedLive(C);
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DAG->addMutation(createLoadClusterDAGMutation(
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DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
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DAG->addMutation(createStoreClusterDAGMutation(
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DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
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}
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const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
311-
if (!DisableVectorMaskMutation && ST.hasVInstructions()) {
312-
DAG = DAG ? DAG : createSchedLive(C);
310+
if (!DisableVectorMaskMutation && ST.hasVInstructions())
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DAG->addMutation(createRISCVVectorMaskDAGMutation(DAG->TRI));
314-
}
312+
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return DAG;
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}
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ScheduleDAGInstrs *
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RISCVTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
320-
ScheduleDAGMI *DAG = nullptr;
318+
ScheduleDAGMI *DAG = createSchedPostRA(C);
321319
if (EnablePostMISchedLoadStoreClustering) {
322-
DAG = createSchedPostRA(C);
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DAG->addMutation(createLoadClusterDAGMutation(
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DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
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DAG->addMutation(createStoreClusterDAGMutation(

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