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1 parent a1d71c3 commit 312c90dCopy full SHA for 312c90d
llvm/test/Transforms/InstCombine/X86/and-sub-combine.ll
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+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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+; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
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+
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+define i8 @and_sub(i8 %a) {
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+; CHECK-LABEL: @and_sub(
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+; CHECK-NEXT: [[AND1:%.*]] = and i8 [[A:%.*]], 15
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+; CHECK-NEXT: [[AND2:%.*]] = and i8 [[A]], 3
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+; CHECK-NEXT: [[RET:%.*]] = sub nsw i8 [[AND1]], [[AND2]]
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+; CHECK-NEXT: ret i8 [[RET]]
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+;
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+ %and1 = and i8 %a, 15
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+ %and2 = and i8 %a, 3
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+ %ret = sub i8 %and1, %and2
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+ ret i8 %ret
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+}
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