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[PowerPC] Implement Vector Shift Builtins
This patch implements the builtins for the vector shifts (shl, srl, sra), and adds the appropriate test cases for these builtins. The builtins utilize the vector shift instructions introduced within ISA 3.1. Differential Revision: https://reviews.llvm.org/D83338
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‎clang/lib/Headers/altivec.h

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@@ -17321,6 +17321,53 @@ vec_test_lsbb_all_zeros(vector unsigned char __a) {
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return __builtin_vsx_xvtlsbb(__a, 0);
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}
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#endif /* __VSX__ */
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/* vs[l | r | ra] */
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static __inline__ vector unsigned __int128 __ATTRS_o_ai
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vec_sl(vector unsigned __int128 __a, vector unsigned __int128 __b) {
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return __a << (__b % (vector unsigned __int128)(sizeof(unsigned __int128) *
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__CHAR_BIT__));
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}
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static __inline__ vector signed __int128 __ATTRS_o_ai
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vec_sl(vector signed __int128 __a, vector unsigned __int128 __b) {
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return __a << (__b % (vector unsigned __int128)(sizeof(unsigned __int128) *
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__CHAR_BIT__));
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}
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static __inline__ vector unsigned __int128 __ATTRS_o_ai
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vec_sr(vector unsigned __int128 __a, vector unsigned __int128 __b) {
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return __a >> (__b % (vector unsigned __int128)(sizeof(unsigned __int128) *
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__CHAR_BIT__));
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}
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static __inline__ vector signed __int128 __ATTRS_o_ai
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vec_sr(vector signed __int128 __a, vector unsigned __int128 __b) {
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return (
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vector signed __int128)(((vector unsigned __int128)__a) >>
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(__b %
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(vector unsigned __int128)(sizeof(
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unsigned __int128) *
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__CHAR_BIT__)));
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}
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static __inline__ vector unsigned __int128 __ATTRS_o_ai
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vec_sra(vector unsigned __int128 __a, vector unsigned __int128 __b) {
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return (
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vector unsigned __int128)(((vector signed __int128)__a) >>
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(__b %
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(vector unsigned __int128)(sizeof(
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unsigned __int128) *
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__CHAR_BIT__)));
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}
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static __inline__ vector signed __int128 __ATTRS_o_ai
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vec_sra(vector signed __int128 __a, vector unsigned __int128 __b) {
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return __a >> (__b % (vector unsigned __int128)(sizeof(unsigned __int128) *
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__CHAR_BIT__));
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}
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#endif /* __POWER10_VECTOR__ */
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#undef __ATTRS_o_ai

‎clang/test/CodeGen/builtins-ppc-p10vector.c

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Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
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#include <altivec.h>
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vector signed __int128 vi128a;
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vector signed char vsca, vscb;
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vector unsigned char vuca, vucb, vucc;
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vector signed short vssa, vssb;
@@ -778,6 +779,49 @@ void test_vec_xst_trunc_ull(vector unsigned __int128 __a, signed long long __b,
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vec_xst_trunc(__a, __b, __c);
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}
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vector unsigned __int128 test_vec_slq_unsigned (void) {
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// CHECK-LABEL: test_vec_slq_unsigned
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// CHECK: shl <1 x i128> %{{.+}}, %{{.+}}
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// CHECK: ret <1 x i128> %{{.+}}
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return vec_sl(vui128a, vui128b);
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}
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vector signed __int128 test_vec_slq_signed (void) {
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// CHECK-LABEL: test_vec_slq_signed
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// CHECK: shl <1 x i128> %{{.+}}, %{{.+}}
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// CHECK: ret <1 x i128>
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return vec_sl(vi128a, vui128a);
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}
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vector unsigned __int128 test_vec_srq_unsigned (void) {
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// CHECK-LABEL: test_vec_srq_unsigned
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// CHECK: lshr <1 x i128> %{{.+}}, %{{.+}}
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// CHECK: ret <1 x i128>
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return vec_sr(vui128a, vui128b);
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}
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vector signed __int128 test_vec_srq_signed (void) {
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// CHECK-LABEL: test_vec_srq_signed
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// CHECK: lshr <1 x i128> %{{.+}}, %{{.+}}
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// CHECK: ret <1 x i128>
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return vec_sr(vi128a, vui128a);
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}
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vector unsigned __int128 test_vec_sraq_unsigned (void) {
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// CHECK-LABEL: test_vec_sraq_unsigned
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// CHECK: ashr <1 x i128> %{{.+}}, %{{.+}}
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// CHECK: ret <1 x i128>
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return vec_sra(vui128a, vui128b);
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}
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vector signed __int128 test_vec_sraq_signed (void) {
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// CHECK-LABEL: test_vec_sraq_signed
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// CHECK: ashr <1 x i128> %{{.+}}, %{{.+}}
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// CHECK: ret <1 x i128>
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return vec_sra(vi128a, vui128a);
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}
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int test_vec_test_lsbb_all_ones(void) {
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// CHECK: @llvm.ppc.vsx.xvtlsbb(<16 x i8> %{{.+}}, i32 1
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// CHECK-NEXT: ret i32

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

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@@ -1128,6 +1128,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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if (Subtarget.has64BitSupport())
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setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
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if (Subtarget.isISA3_1())
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setOperationAction(ISD::SRA, MVT::v1i128, Legal);
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setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
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11331136
if (!isPPC64) {

‎llvm/lib/Target/PowerPC/PPCInstrPrefix.td

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Original file line numberDiff line numberDiff line change
@@ -1288,6 +1288,18 @@ let Predicates = [IsISA3_1] in {
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(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
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def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
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(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
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def : Pat<(v1i128 (shl v1i128:$VRA, v1i128:$VRB)),
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(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
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def : Pat<(v1i128 (PPCshl v1i128:$VRA, v1i128:$VRB)),
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(v1i128 (VSLQ v1i128:$VRA, v1i128:$VRB))>;
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def : Pat<(v1i128 (srl v1i128:$VRA, v1i128:$VRB)),
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(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
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def : Pat<(v1i128 (PPCsrl v1i128:$VRA, v1i128:$VRB)),
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(v1i128 (VSRQ v1i128:$VRA, v1i128:$VRB))>;
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def : Pat<(v1i128 (sra v1i128:$VRA, v1i128:$VRB)),
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(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
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def : Pat<(v1i128 (PPCsra v1i128:$VRA, v1i128:$VRB)),
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(v1i128 (VSRAQ v1i128:$VRA, v1i128:$VRB))>;
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}
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12931305
let AddedComplexity = 400, Predicates = [IsISA3_1] in {

‎llvm/test/CodeGen/PowerPC/p10-vector-shift.ll

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,74 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; These test cases demonstrate that the vector shift quadword instructions
11+
; introduced within Power10 are correctly exploited.
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define dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) {
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; CHECK-LABEL: test_vec_vslq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vslq v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%rem = urem <1 x i128> %b, <i128 128>
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%shl = shl <1 x i128> %a, %rem
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ret <1 x i128> %shl
22+
}
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define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) {
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; CHECK-LABEL: test_vec_vsrq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsrq v2, v2, v3
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; CHECK-NEXT: blr
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entry:
30+
%rem = urem <1 x i128> %b, <i128 128>
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%shr = lshr <1 x i128> %a, %rem
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ret <1 x i128> %shr
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}
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define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) {
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; CHECK-LABEL: test_vec_vsraq:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsraq v2, v2, v3
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; CHECK-NEXT: blr
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entry:
41+
%rem = urem <1 x i128> %b, <i128 128>
42+
%shr = ashr <1 x i128> %a, %rem
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ret <1 x i128> %shr
44+
}
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define dso_local <1 x i128> @test_vec_vslq2(<1 x i128> %a, <1 x i128> %b) {
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; CHECK-LABEL: test_vec_vslq2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vslq v2, v2, v3
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; CHECK-NEXT: blr
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entry:
52+
%shl = shl <1 x i128> %a, %b
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ret <1 x i128> %shl
54+
}
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define dso_local <1 x i128> @test_vec_vsrq2(<1 x i128> %a, <1 x i128> %b) {
57+
; CHECK-LABEL: test_vec_vsrq2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsrq v2, v2, v3
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; CHECK-NEXT: blr
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entry:
62+
%shr = lshr <1 x i128> %a, %b
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ret <1 x i128> %shr
64+
}
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define dso_local <1 x i128> @test_vec_vsraq2(<1 x i128> %a, <1 x i128> %b) {
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; CHECK-LABEL: test_vec_vsraq2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsraq v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%shr = ashr <1 x i128> %a, %b
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ret <1 x i128> %shr
74+
}

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