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antoniofrighettoantoniofrighetto
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[InstCombine] Favour m_Poison in SimplifyDemandedVectorElts
A miscompilation issue has been addressed with refined checking.
1 parent 7b1e423 commit 318d5bf

18 files changed

+143
-131
lines changed

‎llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1350,8 +1350,8 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
13501350
return !isa<PoisonValue>(V) ? PoisonValue::get(V->getType()) : nullptr;
13511351
}
13521352

1353-
if (match(V, m_Undef())) {
1354-
// If the entire vector is undef or poison, just return this info.
1353+
if (match(V, m_Poison())) {
1354+
// If the entire vector is poison, just return this info.
13551355
PoisonElts = EltMask;
13561356
return nullptr;
13571357
}

‎llvm/test/Transforms/InstCombine/X86/clmulqdq.ll

Lines changed: 24 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -51,31 +51,35 @@ define <2 x i64> @test_demanded_elts_pclmulqdq_17(<2 x i64> %a0, <2 x i64> %a1)
5151

5252
define <2 x i64> @test_demanded_elts_pclmulqdq_undef_0() {
5353
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_0(
54-
; CHECK-NEXT: ret <2 x i64> zeroinitializer
54+
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 poison>, <2 x i64> <i64 undef, i64 poison>, i8 0)
55+
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
5556
;
5657
%1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 1>, <2 x i64> <i64 undef, i64 1>, i8 0)
5758
ret <2 x i64> %1
5859
}
5960

6061
define <2 x i64> @test_demanded_elts_pclmulqdq_undef_1() {
6162
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_1(
62-
; CHECK-NEXT: ret <2 x i64> zeroinitializer
63+
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 poison, i64 undef>, <2 x i64> <i64 undef, i64 poison>, i8 1)
64+
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
6365
;
6466
%1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 1, i64 undef>, <2 x i64> <i64 undef, i64 1>, i8 1)
6567
ret <2 x i64> %1
6668
}
6769

6870
define <2 x i64> @test_demanded_elts_pclmulqdq_undef_16() {
6971
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_16(
70-
; CHECK-NEXT: ret <2 x i64> zeroinitializer
72+
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 poison>, <2 x i64> <i64 poison, i64 undef>, i8 16)
73+
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
7174
;
7275
%1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 1>, <2 x i64> <i64 1, i64 undef>, i8 16)
7376
ret <2 x i64> %1
7477
}
7578

7679
define <2 x i64> @test_demanded_elts_pclmulqdq_undef_17() {
7780
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_17(
78-
; CHECK-NEXT: ret <2 x i64> zeroinitializer
81+
; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 poison, i64 undef>, <2 x i64> <i64 poison, i64 undef>, i8 17)
82+
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
7983
;
8084
%1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 1, i64 undef>, <2 x i64> <i64 1, i64 undef>, i8 17)
8185
ret <2 x i64> %1
@@ -135,31 +139,35 @@ define <4 x i64> @test_demanded_elts_pclmulqdq_256_17(<4 x i64> %a0, <4 x i64> %
135139

136140
define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_0() {
137141
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_0(
138-
; CHECK-NEXT: ret <4 x i64> zeroinitializer
142+
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 poison, i64 undef, i64 poison>, <4 x i64> <i64 undef, i64 poison, i64 undef, i64 poison>, i8 0)
143+
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
139144
;
140145
%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, <4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, i8 0)
141146
ret <4 x i64> %1
142147
}
143148

144149
define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_1() {
145150
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_1(
146-
; CHECK-NEXT: ret <4 x i64> zeroinitializer
151+
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 poison, i64 undef, i64 poison, i64 undef>, <4 x i64> <i64 undef, i64 poison, i64 undef, i64 poison>, i8 1)
152+
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
147153
;
148154
%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, <4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, i8 1)
149155
ret <4 x i64> %1
150156
}
151157

152158
define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_16() {
153159
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_16(
154-
; CHECK-NEXT: ret <4 x i64> zeroinitializer
160+
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 poison, i64 undef, i64 poison>, <4 x i64> <i64 poison, i64 undef, i64 poison, i64 undef>, i8 16)
161+
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
155162
;
156163
%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, <4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, i8 16)
157164
ret <4 x i64> %1
158165
}
159166

160167
define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_17() {
161168
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_17(
162-
; CHECK-NEXT: ret <4 x i64> zeroinitializer
169+
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 poison, i64 undef, i64 poison, i64 undef>, <4 x i64> <i64 poison, i64 undef, i64 poison, i64 undef>, i8 17)
170+
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
163171
;
164172
%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, <4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, i8 17)
165173
ret <4 x i64> %1
@@ -235,31 +243,35 @@ define <8 x i64> @test_demanded_elts_pclmulqdq_512_17(<8 x i64> %a0, <8 x i64> %
235243

236244
define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_0() {
237245
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_0(
238-
; CHECK-NEXT: ret <8 x i64> zeroinitializer
246+
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison>, <8 x i64> <i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison>, i8 0)
247+
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
239248
;
240249
%1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, <8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, i8 0)
241250
ret <8 x i64> %1
242251
}
243252

244253
define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_1() {
245254
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_1(
246-
; CHECK-NEXT: ret <8 x i64> zeroinitializer
255+
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef>, <8 x i64> <i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison>, i8 1)
256+
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
247257
;
248258
%1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, <8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, i8 1)
249259
ret <8 x i64> %1
250260
}
251261

252262
define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_16() {
253263
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_16(
254-
; CHECK-NEXT: ret <8 x i64> zeroinitializer
264+
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison>, <8 x i64> <i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef>, i8 16)
265+
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
255266
;
256267
%1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, <8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, i8 16)
257268
ret <8 x i64> %1
258269
}
259270

260271
define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_17() {
261272
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_17(
262-
; CHECK-NEXT: ret <8 x i64> zeroinitializer
273+
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef>, <8 x i64> <i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef>, i8 17)
274+
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
263275
;
264276
%1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, <8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, i8 17)
265277
ret <8 x i64> %1

‎llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) {
2323
define <4 x float> @test_add_ss_round(<4 x float> %a, <4 x float> %b) {
2424
;
2525
; CHECK-LABEL: @test_add_ss_round(
26-
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
26+
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
2727
; CHECK-NEXT: ret <4 x float> [[TMP1]]
2828
;
2929
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -103,7 +103,7 @@ define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) {
103103
define <2 x double> @test_add_sd_round(<2 x double> %a, <2 x double> %b) {
104104
;
105105
; CHECK-LABEL: @test_add_sd_round(
106-
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
106+
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
107107
; CHECK-NEXT: ret <2 x double> [[TMP1]]
108108
;
109109
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -175,7 +175,7 @@ define <4 x float> @test_sub_ss(<4 x float> %a, <4 x float> %b) {
175175
define <4 x float> @test_sub_ss_round(<4 x float> %a, <4 x float> %b) {
176176
;
177177
; CHECK-LABEL: @test_sub_ss_round(
178-
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
178+
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
179179
; CHECK-NEXT: ret <4 x float> [[TMP1]]
180180
;
181181
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -255,7 +255,7 @@ define <2 x double> @test_sub_sd(<2 x double> %a, <2 x double> %b) {
255255
define <2 x double> @test_sub_sd_round(<2 x double> %a, <2 x double> %b) {
256256
;
257257
; CHECK-LABEL: @test_sub_sd_round(
258-
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
258+
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
259259
; CHECK-NEXT: ret <2 x double> [[TMP1]]
260260
;
261261
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -327,7 +327,7 @@ define <4 x float> @test_mul_ss(<4 x float> %a, <4 x float> %b) {
327327
define <4 x float> @test_mul_ss_round(<4 x float> %a, <4 x float> %b) {
328328
;
329329
; CHECK-LABEL: @test_mul_ss_round(
330-
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
330+
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
331331
; CHECK-NEXT: ret <4 x float> [[TMP1]]
332332
;
333333
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -407,7 +407,7 @@ define <2 x double> @test_mul_sd(<2 x double> %a, <2 x double> %b) {
407407
define <2 x double> @test_mul_sd_round(<2 x double> %a, <2 x double> %b) {
408408
;
409409
; CHECK-LABEL: @test_mul_sd_round(
410-
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
410+
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
411411
; CHECK-NEXT: ret <2 x double> [[TMP1]]
412412
;
413413
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -479,7 +479,7 @@ define <4 x float> @test_div_ss(<4 x float> %a, <4 x float> %b) {
479479
define <4 x float> @test_div_ss_round(<4 x float> %a, <4 x float> %b) {
480480
;
481481
; CHECK-LABEL: @test_div_ss_round(
482-
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
482+
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
483483
; CHECK-NEXT: ret <4 x float> [[TMP1]]
484484
;
485485
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -559,7 +559,7 @@ define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) {
559559
define <2 x double> @test_div_sd_round(<2 x double> %a, <2 x double> %b) {
560560
;
561561
; CHECK-LABEL: @test_div_sd_round(
562-
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
562+
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
563563
; CHECK-NEXT: ret <2 x double> [[TMP1]]
564564
;
565565
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -615,7 +615,7 @@ declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>,
615615
define <4 x float> @test_max_ss(<4 x float> %a, <4 x float> %b) {
616616
;
617617
; CHECK-LABEL: @test_max_ss(
618-
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 4)
618+
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 4)
619619
; CHECK-NEXT: ret <4 x float> [[TMP1]]
620620
;
621621
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -661,7 +661,7 @@ declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x doubl
661661
define <2 x double> @test_max_sd(<2 x double> %a, <2 x double> %b) {
662662
;
663663
; CHECK-LABEL: @test_max_sd(
664-
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 4)
664+
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 4)
665665
; CHECK-NEXT: ret <2 x double> [[TMP1]]
666666
;
667667
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
@@ -699,7 +699,7 @@ declare <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float>, <4 x float>,
699699
define <4 x float> @test_min_ss(<4 x float> %a, <4 x float> %b) {
700700
;
701701
; CHECK-LABEL: @test_min_ss(
702-
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 4)
702+
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 4)
703703
; CHECK-NEXT: ret <4 x float> [[TMP1]]
704704
;
705705
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
@@ -745,7 +745,7 @@ declare <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double>, <2 x doubl
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define <2 x double> @test_min_sd(<2 x double> %a, <2 x double> %b) {
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;
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; CHECK-LABEL: @test_min_sd(
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; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 4)
748+
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 4)
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; CHECK-NEXT: ret <2 x double> [[TMP1]]
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;
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%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1

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