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amilendraamilendra
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[AArch64][v8.7-A] Fix inconsistency in SPE_EEF feature (#115296)
The `SPE-EEF` system-register only feature introduced in Armv8.7-a adds support for an extra system register (`PMSNEVFR_EL1`) to the Statistical Profiling extension. However, `SPE-EEF` is gated even for Armv8.7-a and the `spe-eef` subtarget-feature is needed to enable it. This behavior is inconsistent with the implementation for other system-register only features as they can be used ungated under supported architectures. (e.g. HCX : Enable Armv8.7-A `HCRX_EL2` system register). GCC/Binutils too do not add command line flags for features that only enable system registers. Fix by enabling `SPE-EEF` unconditionally under v8.7-A and above.
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‎clang/test/Driver/print-enabled-extensions/aarch64-ampere1b.c

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@@ -51,6 +51,7 @@
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// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support
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// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
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// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension

‎clang/test/Driver/print-enabled-extensions/aarch64-apple-m4.c

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// CHECK-NEXT: FEAT_SME_F64F64 Enable Scalable Matrix Extension (SME) F64F64 instructions
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// CHECK-NEXT: FEAT_SME_I16I64 Enable Scalable Matrix Extension (SME) I16I64 instructions
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
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// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension
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// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState

‎clang/test/Driver/print-enabled-extensions/aarch64-armv8.7-a.c

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// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
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// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension

‎clang/test/Driver/print-enabled-extensions/aarch64-armv8.8-a.c

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// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
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// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension

‎clang/test/Driver/print-enabled-extensions/aarch64-armv8.9-a.c

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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPECRES2 Enable Speculation Restriction Instruction
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions
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// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension

‎clang/test/Driver/print-enabled-extensions/aarch64-armv9.2-a.c

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// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
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// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions

‎clang/test/Driver/print-enabled-extensions/aarch64-armv9.3-a.c

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// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
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// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions

‎clang/test/Driver/print-enabled-extensions/aarch64-armv9.4-a.c

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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPECRES2 Enable Speculation Restriction Instruction
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
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// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions

‎clang/test/Driver/print-enabled-extensions/aarch64-armv9.5-a.c

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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPECRES2 Enable Speculation Restriction Instruction
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
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// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions

‎clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520.c

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// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
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// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions

‎clang/test/Driver/print-enabled-extensions/aarch64-cortex-a520ae.c

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// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier
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// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension
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// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions
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// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension
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// CHECK-NEXT: FEAT_SSBS, FEAT_SSBS2 Enable Speculative Store Bypass Safe bit
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// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions
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// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions

‎llvm/lib/Target/AArch64/AArch64Features.td

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@@ -847,7 +847,7 @@ def HasV8_6aOps : Architecture64<8, 6, "a", "v8.6a",
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FeatureEnhancedCounterVirtualization, FeatureMatMulInt8],
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!listconcat(HasV8_5aOps.DefaultExts, [FeatureBF16, FeatureMatMulInt8])>;
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def HasV8_7aOps : Architecture64<8, 7, "a", "v8.7a",
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[HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX],
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[HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX, FeatureSPE_EEF],
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!listconcat(HasV8_6aOps.DefaultExts, [FeatureWFxT])>;
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def HasV8_8aOps : Architecture64<8, 8, "a", "v8.8a",
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[HasV8_7aOps, FeatureHBC, FeatureMOPS, FeatureNMI],

‎llvm/test/MC/AArch64/spe.s

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// RUN: llvm-mc -triple aarch64 -mattr +spe-eef -show-encoding %s 2>%t | FileCheck %s
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// RUN: llvm-mc -triple aarch64 -mattr +v8.7a -show-encoding %s 2>%t | FileCheck %s
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// RUN: not llvm-mc -triple aarch64 < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-SPE-EEF-ERR %s
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msr PMSNEVFR_EL1, x0
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mrs x1, PMSNEVFR_EL1
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// CHECK: msr PMSNEVFR_EL1, x0 // encoding: [0x20,0x99,0x18,0xd5]
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// CHECK: mrs x1, PMSNEVFR_EL1 // encoding: [0x21,0x99,0x38,0xd5]
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// CHECK-NO-SPE-EEF-ERR: [[@LINE-5]]:5: error: expected writable system register or pstate
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// CHECK-NO-SPE-EEF-ERR: [[@LINE-5]]:9: error: expected readable system register

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