!fixup move from custom legalization to LegalizerHelper::lower

Author: michaelmaitland

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

@@ -430,6 +430,7 @@ class LegalizerHelper {
   LegalizeResult lowerVectorReduction(MachineInstr &MI);
   LegalizeResult lowerMemcpyInline(MachineInstr &MI);
   LegalizeResult lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen = 0);
+  LegalizeResult lowerPtrMask(MachineInstr &MI);
 };
 
 /// Helper function that creates a libcall to the given \p Name using the given

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

@@ -3780,6 +3780,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
     return lowerTRUNC(MI);
   GISEL_VECREDUCE_CASES_NONSEQ
     return lowerVectorReduction(MI);
+  case G_PTRMASK:
+    return lowerPtrMask(MI);
   }
 }
 
@@ -8405,3 +8407,20 @@ LegalizerHelper::lowerMemCpyFamily(MachineInstr &MI, unsigned MaxLen) {
     return lowerMemset(MI, Dst, Src, KnownLen, DstAlign, IsVolatile);
   return UnableToLegalize;
 }
+
+LegalizerHelper::LegalizeResult
+LegalizerHelper::lowerPtrMask(MachineInstr &MI) {
+  assert(MI.getOpcode() == TargetOpcode::G_PTRMASK);
+
+  MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
+  Register Tmp1 =
+      MRI.createGenericVirtualRegister(MRI.getType(MI.getOperand(2).getReg()));
+  Register Tmp2 =
+      MRI.createGenericVirtualRegister(MRI.getType(MI.getOperand(2).getReg()));
+  MIRBuilder.buildPtrToInt(Tmp1, MI.getOperand(1).getReg());
+  MIRBuilder.buildAnd(Tmp2, Tmp1, MI.getOperand(2).getReg());
+  MIRBuilder.buildIntToPtr(MI.getOperand(0).getReg(), Tmp2);
+
+  MI.eraseFromParent();
+  return Legalized;
+}

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

@@ -147,7 +147,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
 
   getActionDefinitionsBuilder(G_PTR_ADD).legalFor({{p0, sXLen}});
 
-  getActionDefinitionsBuilder(G_PTRMASK).customFor({{p0, sXLen}});
+  getActionDefinitionsBuilder(G_PTRMASK).lowerFor({{p0, sXLen}});
 
   getActionDefinitionsBuilder(G_PTRTOINT)
       .legalFor({{sXLen, p0}})
@@ -290,25 +290,6 @@ bool RISCVLegalizerInfo::legalizeShlAshrLshr(
   return true;
 }
 
-bool RISCVLegalizerInfo::legalizePtrMask(MachineInstr &MI,
-                                         MachineIRBuilder &MIRBuilder,
-                                         GISelChangeObserver &Observer) const {
-  assert(MI.getOpcode() == TargetOpcode::G_PTRMASK);
-
-  MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
-  Register Tmp1 =
-      MRI.createGenericVirtualRegister(MRI.getType(MI.getOperand(2).getReg()));
-  Register Tmp2 =
-      MRI.createGenericVirtualRegister(MRI.getType(MI.getOperand(2).getReg()));
-  MIRBuilder.buildPtrToInt(Tmp1, MI.getOperand(1).getReg());
-  MIRBuilder.buildAnd(Tmp2, Tmp1, MI.getOperand(2).getReg());
-  MIRBuilder.buildIntToPtr(MI.getOperand(0).getReg(), Tmp2);
-
-  Observer.erasingInstr(MI);
-  MI.eraseFromParent();
-  return true;
-}
-
 bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
                                         MachineInstr &MI) const {
   MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
@@ -330,9 +311,6 @@ bool RISCVLegalizerInfo::legalizeCustom(LegalizerHelper &Helper,
     return Helper.lower(MI, 0, /* Unused hint type */ LLT()) ==
            LegalizerHelper::Legalized;
   }
-  case TargetOpcode::G_PTRMASK:
-    return legalizePtrMask(MI, MIRBuilder, Observer);
   }
-
   llvm_unreachable("expected switch to return");
 }

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h

@@ -31,9 +31,6 @@ class RISCVLegalizerInfo : public LegalizerInfo {
 private:
   bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
                            GISelChangeObserver &Observer) const;
-
-  bool legalizePtrMask(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
-                       GISelChangeObserver &Observer) const;
 };
 } // end namespace llvm
 #endif